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/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
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H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial ATA AHCI controllers
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
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H A Dahci-platform.txt1 * AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
6 It is possible, but not required, to represent each port as a sub-node.
7 It allows to enable each port independently when dealing with multiple
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
16 - "marvell,armada-380-ahci"
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H A Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
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H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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H A Dsnps,dwc-ahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10 - Serge Semin <fancer.lancer@gmail.com>
14 AHCI controller properties.
19 - $ref: ahci-common.yaml#
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
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H A Dbrcm,sata-brcm.txt1 * Broadcom SATA3 AHCI Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : should be one or more of
8 "brcm,bcm7216-ahci"
9 "brcm,bcm7425-ahci"
10 "brcm,bcm7445-ahci"
11 "brcm,bcm-nsp-ahci"
12 "brcm,sata3-ahci"
13 "brcm,bcm63138-ahci"
14 - reg : register mappings for AHCI and SATA_TOP_CTRL
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H A Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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H A Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
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H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci
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H A Dahci-ceva.txt1 Binding for CEVA AHCI SATA Controller
4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
6 - clocks: Input clock specifier. Refer to common clock bindings.
7 - interrupts: Interrupt specifier. Refer to interrupt binding.
8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
11 ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
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H A Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
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H A Dahci-mtk.txt4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
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H A Dqcom-sata.txt1 * Qualcomm AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
15 - clocks : Must contain an entry for each entry in clock-names.
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H A Dahci-st.txt6 - compatible : Must be "st,ahci"
7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc"
10 - clocks : The phandle for the clock
11 - clock-names : Associated name must be; "ahci_clk"
12 - phys : The phandle for the PHY port
13 - phy-names : Associated name must be; "ahci_phy"
16 - resets : The power-down, soft-reset and power-reset lines of SATA IP
17 - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
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/freebsd/share/man/man4/
H A Dahci.41 .\" Copyright (c) 2009-2013 Alexander Motin <mav@FreeBSD.org>
29 .Nm ahci
35 .Bd -ragged -offset indent
38 .Cd "device ahci"
44 .Bd -literal -offset indent
50 .Bl -ohang
51 .It Va hint.ahci. Ns Ar X Ns Va .msi
54 .Bl -tag -width 4n -offset indent -compact
62 .It Va hint.ahci. Ns Ar X Ns Va .ccc
64 Non-zero value enables CCC and defines maximum time (in ms), request can wait
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H A Data.434 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
73 The next three lines are generic bus-specific drivers.
74 The rest are vendor-specific PCI drivers.
78 .Bl -ohang
93 .Bl -tag -width 4n -offset indent -compact
115 port or each one or two SATA ports are
117 Most of the bus-management details are handled by the ATA/SATA-specific
128 Command queuing and SATA port multipliers are not supported.
129 Device hot-plug and SATA interface power management is supported only on
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-sata.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
39 sata0: ahci@0 {
40 compatible = "brcm,iproc-ahci", "generic-ahci";
42 reg-names = "ahci";
44 #address-cells = <1>;
45 #size-cells = <0>;
48 sata0_port0: sata-port@0 {
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/freebsd/usr.sbin/bhyve/
H A Dbhyve.860 .Ar port
99 I/O connectivity can be specified with command-line parameters.
110 .Pa edk2-bhyve
113 .Pa u-boot-bhyve-arm64
114 package provides a U-Boot image that can be used to boot the guest.
120 .Bl -tag -width 10n
161 Destroy the VM on guest initiated power-off.
165 to exit when a guest issues an access to an I/O port that is not emulated.
181 .Ar port
189 .Ar port
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H A Dbhyve_config.51 .\" SPDX-License-Identifier: BSD-2-Clause
35 per-device settings.
69 For those variables the following case-insensitive values may be used to
72 .Bl -bullet -offset indent -compact
85 .Bl -bullet -offset indent -compact
103 .Bl -column "memory.guest_in_core" "integer" "Default"
140 This can cause problems if the guest uses the in-memory version, since certain
144 Destroy the VM on guest-initiated power-off.
147 .It Va gdb.port Ta integer Ta 0 Ta
148 TCP port number for the debug server.
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H A Dpci_ahci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
60 #include "ahci.h"
63 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
64 #define MAX_PORTS 32 /* AHCI supports 32 ports */
70 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
71 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
72 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
73 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
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/freebsd/sys/dev/ahci/
H A Dahci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
45 #include "ahci.h"
96 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
108 return ch->disablephy ? ATA_SC_DET_DISABLE : val; in ahci_ch_detval()
116 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); in ahci_ctlr_setup()
118 if (ctlr->ccc) { in ahci_ctlr_setup()
119 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); in ahci_ctlr_setup()
120 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, in ahci_ctlr_setup()
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cell
150 ahci: sata@a000 { global() label
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/freebsd/sys/contrib/device-tree/src/arm/socionext/
H A Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
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