Lines Matching +full:ahci +full:- +full:port

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10   - Serge Semin <fancer.lancer@gmail.com>
14   AHCI controller properties.
19   - $ref: ahci-common.yaml#
30       Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31       PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
36   clock-names:
41         - description: Application APB/AHB/AXI BIU clock
43             - pclk
44             - aclk
45             - hclk
46             - sata
47         - description: Power Module keep-alive clock
49         - description: RxOOB detection clock
51         - description: PHY Transmit Clock
53         - description: PHY Receive Clock
55         - description: SATA Ports reference clock
61       normally supported by the DWC AHCI SATA controller.
65   reset-names:
70         - description: Application AHB/AXI BIU clock domain reset control
72             - arst
73             - hrst
74         - description: Power Module keep-alive clock domain reset control
76         - description: RxOOB detection clock domain reset control
78         - description: Reference clock domain reset control
82   "^sata-port@[0-9a-e]$":
83     $ref: '#/$defs/dwc-ahci-port'
88   dwc-ahci-port:
89     $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
96       snps,tx-ts-max:
101       snps,rx-ts-max: