Lines Matching +full:ahci +full:- +full:port

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10   The Calxeda SATA controller mostly conforms to the AHCI interface
15   - Andre Przywara <andre.przywara@arm.com>
19     const: calxeda,hb-ahci
27   dma-coherent: true
29   calxeda,pre-clocks:
35   calxeda,post-clocks:
41   calxeda,led-order:
42     description: Maps port numbers to offsets within the SGPIO bitstream.
43     $ref: /schemas/types.yaml#/definitions/uint32-array
47   calxeda,port-phys:
49       phandle-combophy and lane assignment, which maps each SATA port to a
51     $ref: /schemas/types.yaml#/definitions/phandle-array
57   calxeda,tx-atten:
59       Contains TX attenuation override codes, one per port.
61     $ref: /schemas/types.yaml#/definitions/uint32-array
65   calxeda,sgpio-gpio:
68       phandle-gpio bank, bit offset, and default on or off, which indicates
73   - compatible
74   - reg
75   - interrupts
80   - |
82         compatible = "calxeda,hb-ahci";
85         dma-coherent;
86         calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
88         calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
89         calxeda,led-order = <4 0 1 2 3>;
90         calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
91         calxeda,pre-clocks = <10>;
92         calxeda,post-clocks = <0>;