Lines Matching +full:ahci +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a9";
26 enable-method = "psci";
27 next-level-cache = <&l2>;
28 operating-points-v2 = <&cpu_opp>;
29 #cooling-cells = <2>;
34 compatible = "arm,cortex-a9";
37 enable-method = "psci";
38 next-level-cache = <&l2>;
39 operating-points-v2 = <&cpu_opp>;
40 #cooling-cells = <2>;
45 compatible = "arm,cortex-a9";
48 enable-method = "psci";
49 next-level-cache = <&l2>;
50 operating-points-v2 = <&cpu_opp>;
51 #cooling-cells = <2>;
56 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu_opp>;
62 #cooling-cells = <2>;
66 cpu_opp: opp-table {
67 compatible = "operating-points-v2";
68 opp-shared;
70 opp-100000000 {
71 opp-hz = /bits/ 64 <100000000>;
72 clock-latency-ns = <300>;
74 opp-150000000 {
75 opp-hz = /bits/ 64 <150000000>;
76 clock-latency-ns = <300>;
78 opp-200000000 {
79 opp-hz = /bits/ 64 <200000000>;
80 clock-latency-ns = <300>;
82 opp-300000000 {
83 opp-hz = /bits/ 64 <300000000>;
84 clock-latency-ns = <300>;
86 opp-400000000 {
87 opp-hz = /bits/ 64 <400000000>;
88 clock-latency-ns = <300>;
90 opp-600000000 {
91 opp-hz = /bits/ 64 <600000000>;
92 clock-latency-ns = <300>;
94 opp-800000000 {
95 opp-hz = /bits/ 64 <800000000>;
96 clock-latency-ns = <300>;
98 opp-1200000000 {
99 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <300>;
105 compatible = "arm,psci-0.2";
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <25000000>;
116 arm_timer_clk: arm-timer {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <50000000>;
123 thermal-zones {
124 cpu-thermal {
125 polling-delay-passive = <250>; /* 250ms */
126 polling-delay = <1000>; /* 1000ms */
127 thermal-sensors = <&pvtctl>;
130 cpu_crit: cpu-crit {
135 cpu_alert: cpu-alert {
142 cooling-maps {
145 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
159 interrupt-parent = <&intc>;
161 l2: cache-controller@500c0000 {
162 compatible = "socionext,uniphier-system-cache";
169 cache-unified;
170 cache-size = <(1280 * 1024)>;
171 cache-sets = <512>;
172 cache-line-size = <128>;
173 cache-level = <2>;
177 compatible = "socionext,uniphier-scssi";
180 #address-cells = <1>;
181 #size-cells = <0>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_spi0>;
190 compatible = "socionext,uniphier-scssi";
193 #address-cells = <1>;
194 #size-cells = <0>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_spi1>;
203 compatible = "socionext,uniphier-uart";
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart0>;
214 compatible = "socionext,uniphier-uart";
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_uart1>;
225 compatible = "socionext,uniphier-uart";
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_uart2>;
236 compatible = "socionext,uniphier-uart";
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_uart3>;
247 compatible = "socionext,uniphier-gpio";
249 interrupt-parent = <&aidet>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 gpio-ranges = <&pinctrl 0 0 0>,
256 gpio-ranges-group-names = "gpio_range0",
259 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
264 compatible = "socionext,uniphier-pxs2-aio";
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_ain1>,
275 clock-names = "aio";
277 reset-names = "aio";
279 #sound-dai-cells = <1>;
282 i2s_port0: port@0 {
287 i2s_port1: port@1 {
292 i2s_port2: port@2 {
297 spdif_port0: port@3 {
302 spdif_port1: port@4 {
307 comp_spdif_port0: port@5 {
312 comp_spdif_port1: port@6 {
319 compatible = "socionext,uniphier-fi2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_i2c0>;
329 clock-frequency = <100000>;
333 compatible = "socionext,uniphier-fi2c";
336 #address-cells = <1>;
337 #size-cells = <0>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_i2c1>;
343 clock-frequency = <100000>;
347 compatible = "socionext,uniphier-fi2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_i2c2>;
357 clock-frequency = <100000>;
361 compatible = "socionext,uniphier-fi2c";
364 #address-cells = <1>;
365 #size-cells = <0>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_i2c3>;
371 clock-frequency = <100000>;
374 /* chip-internal connection for DMD */
376 compatible = "socionext,uniphier-fi2c";
378 #address-cells = <1>;
379 #size-cells = <0>;
383 clock-frequency = <400000>;
386 /* chip-internal connection for STM */
388 compatible = "socionext,uniphier-fi2c";
390 #address-cells = <1>;
391 #size-cells = <0>;
395 clock-frequency = <400000>;
398 /* chip-internal connection for HDMI */
400 compatible = "socionext,uniphier-fi2c";
402 #address-cells = <1>;
403 #size-cells = <0>;
407 clock-frequency = <400000>;
410 system_bus: system-bus@58c00000 {
411 compatible = "socionext,uniphier-system-bus";
414 #address-cells = <2>;
415 #size-cells = <1>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_system_bus>;
421 compatible = "socionext,uniphier-smpctrl";
426 compatible = "socionext,uniphier-pxs2-sdctrl",
427 "simple-mfd", "syscon";
430 sd_clk: clock-controller {
431 compatible = "socionext,uniphier-pxs2-sd-clock";
432 #clock-cells = <1>;
435 sd_rst: reset-controller {
436 compatible = "socionext,uniphier-pxs2-sd-reset";
437 #reset-cells = <1>;
442 compatible = "socionext,uniphier-pxs2-perictrl",
443 "simple-mfd", "syscon";
446 peri_clk: clock-controller {
447 compatible = "socionext,uniphier-pxs2-peri-clock";
448 #clock-cells = <1>;
451 peri_rst: reset-controller {
452 compatible = "socionext,uniphier-pxs2-peri-reset";
453 #reset-cells = <1>;
458 compatible = "socionext,uniphier-sd-v3.1.1";
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_emmc>;
465 reset-names = "host", "hw";
467 bus-width = <8>;
468 cap-mmc-highspeed;
469 cap-mmc-hw-reset;
470 non-removable;
474 compatible = "socionext,uniphier-sd-v3.1.1";
478 pinctrl-names = "default", "uhs";
479 pinctrl-0 = <&pinctrl_sd>;
480 pinctrl-1 = <&pinctrl_sd_uhs>;
482 reset-names = "host";
484 bus-width = <4>;
485 cap-sd-highspeed;
486 sd-uhs-sdr12;
487 sd-uhs-sdr25;
488 sd-uhs-sdr50;
489 socionext,syscon-uhs-mode = <&sdctrl 0>;
493 compatible = "socionext,uniphier-pxs2-soc-glue",
494 "simple-mfd", "syscon";
498 compatible = "socionext,uniphier-pxs2-pinctrl";
503 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
504 "simple-mfd", "syscon";
506 #address-cells = <1>;
507 #size-cells = <1>;
511 compatible = "socionext,uniphier-efuse";
516 compatible = "socionext,uniphier-efuse";
521 xdmac: dma-controller@5fc10000 {
522 compatible = "socionext,uniphier-xdmac";
525 dma-channels = <16>;
526 #dma-cells = <2>;
529 aidet: interrupt-controller@5fc20000 {
530 compatible = "socionext,uniphier-pxs2-aidet";
532 interrupt-controller;
533 #interrupt-cells = <2>;
537 compatible = "arm,cortex-a9-global-timer";
545 compatible = "arm,cortex-a9-twd-timer";
552 intc: interrupt-controller@60001000 {
553 compatible = "arm,cortex-a9-gic";
556 #interrupt-cells = <3>;
557 interrupt-controller;
561 compatible = "socionext,uniphier-pxs2-sysctrl",
562 "simple-mfd", "syscon";
565 sys_clk: clock-controller {
566 compatible = "socionext,uniphier-pxs2-clock";
567 #clock-cells = <1>;
570 sys_rst: reset-controller {
571 compatible = "socionext,uniphier-pxs2-reset";
572 #reset-cells = <1>;
575 pvtctl: thermal-sensor {
576 compatible = "socionext,uniphier-pxs2-thermal";
578 #thermal-sensor-cells = <0>;
579 socionext,tmod-calibration = <0x0f86 0x6844>;
584 compatible = "socionext,uniphier-pxs2-ave4";
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_ether_rgmii>;
590 clock-names = "ether";
592 reset-names = "ether";
594 phy-mode = "rgmii-id";
595 local-mac-address = [00 00 00 00 00 00];
596 socionext,syscon-phy-mode = <&soc_glue 0>;
599 #address-cells = <1>;
600 #size-cells = <0>;
604 ahci: sata@65600000 { label
605 compatible = "socionext,uniphier-pxs2-ahci",
606 "generic-ahci";
612 ports-implemented = <1>;
616 sata-controller@65700000 {
617 compatible = "socionext,uniphier-pxs2-ahci-glue",
618 "simple-mfd";
620 #address-cells = <1>;
621 #size-cells = <1>;
624 ahci_rst: reset-controller@0 {
625 compatible = "socionext,uniphier-pxs2-ahci-reset";
627 clock-names = "link";
629 reset-names = "link";
631 #reset-cells = <1>;
635 compatible = "socionext,uniphier-pxs2-ahci-phy";
637 clock-names = "link";
639 reset-names = "link", "phy";
641 #phy-cells = <0>;
646 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
649 interrupt-names = "dwc_usb3";
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
653 clock-names = "ref", "bus_early", "suspend";
661 usb-controller@65b00000 {
662 compatible = "socionext,uniphier-pxs2-dwc3-glue",
663 "simple-mfd";
665 #address-cells = <1>;
666 #size-cells = <1>;
669 usb0_rst: reset-controller@0 {
670 compatible = "socionext,uniphier-pxs2-usb3-reset";
672 #reset-cells = <1>;
673 clock-names = "link";
675 reset-names = "link";
680 compatible = "socionext,uniphier-pxs2-usb3-regulator";
682 clock-names = "link";
684 reset-names = "link";
689 compatible = "socionext,uniphier-pxs2-usb3-regulator";
691 clock-names = "link";
693 reset-names = "link";
698 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
700 #phy-cells = <0>;
701 clock-names = "link", "phy";
703 reset-names = "link", "phy";
705 vbus-supply = <&usb0_vbus0>;
709 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
711 #phy-cells = <0>;
712 clock-names = "link", "phy";
714 reset-names = "link", "phy";
716 vbus-supply = <&usb0_vbus1>;
720 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
722 #phy-cells = <0>;
723 clock-names = "link", "phy";
725 reset-names = "link", "phy";
727 vbus-supply = <&usb0_vbus0>;
731 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
733 #phy-cells = <0>;
734 clock-names = "link", "phy";
736 reset-names = "link", "phy";
738 vbus-supply = <&usb0_vbus1>;
743 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
746 interrupt-names = "dwc_usb3";
748 pinctrl-names = "default";
749 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
750 clock-names = "ref", "bus_early", "suspend";
757 usb-controller@65d00000 {
758 compatible = "socionext,uniphier-pxs2-dwc3-glue",
759 "simple-mfd";
761 #address-cells = <1>;
762 #size-cells = <1>;
765 usb1_rst: reset-controller@0 {
766 compatible = "socionext,uniphier-pxs2-usb3-reset";
768 #reset-cells = <1>;
769 clock-names = "link";
771 reset-names = "link";
776 compatible = "socionext,uniphier-pxs2-usb3-regulator";
778 clock-names = "link";
780 reset-names = "link";
785 compatible = "socionext,uniphier-pxs2-usb3-regulator";
787 clock-names = "link";
789 reset-names = "link";
794 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
796 #phy-cells = <0>;
797 clock-names = "link", "phy";
799 reset-names = "link", "phy";
801 vbus-supply = <&usb1_vbus0>;
805 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
807 #phy-cells = <0>;
808 clock-names = "link", "phy";
810 reset-names = "link", "phy";
812 vbus-supply = <&usb1_vbus1>;
816 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
818 #phy-cells = <0>;
819 clock-names = "link", "phy";
821 reset-names = "link", "phy";
823 vbus-supply = <&usb1_vbus0>;
827 nand: nand-controller@68000000 {
828 compatible = "socionext,uniphier-denali-nand-v5b";
830 reg-names = "nand_data", "denali_reg";
832 #address-cells = <1>;
833 #size-cells = <0>;
835 pinctrl-names = "default";
836 pinctrl-0 = <&pinctrl_nand>;
837 clock-names = "nand", "nand_x", "ecc";
839 reset-names = "nand", "reg";
845 #include "uniphier-pinctrl.dtsi"