Lines Matching +full:ahci +full:- +full:port

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10   - Serge Semin <fancer.lancer@gmail.com>
14   implementation of the AHCI SATA controller found in Rockchip
22           - rockchip,rk3568-dwc-ahci
23           - rockchip,rk3588-dwc-ahci
25     - compatible
30       - enum:
31           - rockchip,rk3568-dwc-ahci
32           - rockchip,rk3588-dwc-ahci
33       - const: snps,dwc-ahci
35   ports-implemented:
38   sata-port@0:
39     $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
48   "^sata-port@[1-9a-e]$": false
51   - compatible
52   - reg
53   - interrupts
54   - clocks
55   - clock-names
56   - ports-implemented
59   - $ref: snps,dwc-ahci-common.yaml#
60   - if:
65               - rockchip,rk3588-dwc-ahci
70         clock-names:
72             - const: sata
73             - const: pmalive
74             - const: rxoob
75             - const: ref
76             - const: asic
77   - if:
82               - rockchip,rk3568-dwc-ahci
87         clock-names:
89             - const: sata
90             - const: pmalive
91             - const: rxoob
96   - |
97     #include <dt-bindings/clock/rockchip,rk3588-cru.h>
98     #include <dt-bindings/interrupt-controller/arm-gic.h>
99     #include <dt-bindings/ata/ahci.h>
100     #include <dt-bindings/phy/phy.h>
103       compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
108       clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
110       ports-implemented = <0x1>;
111       #address-cells = <1>;
112       #size-cells = <0>;
114       sata-port@0 {
116         hba-port-cap = <HBA_PORT_FBSCP>;
118         phy-names = "sata-phy";
119         snps,rx-ts-max = <32>;
120         snps,tx-ts-max = <32>;