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/linux/lib/zlib_inflate/
H A Dinffixed.h1 /* inffixed.h -- table for decoding fixed codes
11 {96,7,0},{0,8,80},{0,8,16},{20,8,115},{18,7,31},{0,8,112},{0,8,48},
12 {0,9,192},{16,7,10},{0,8,96},{0,8,32},{0,9,160},{0,8,0},{0,8,128},
13 {0,8,64},{0,9,224},{16,7,6},{0,8,88},{0,8,24},{0,9,144},{19,7,59},
14 {0,8,120},{0,8,56},{0,9,208},{17,7,17},{0,8,104},{0,8,40},{0,9,176},
15 {0,8,8},{0,8,136},{0,8,72},{0,9,240},{16,7,4},{0,8,84},{0,8,20},
16 {21,8,227},{19,7,43},{0,8,116},{0,8,52},{0,9,200},{17,7,13},{0,8,100},
17 {0,8,36},{0,9,168},{0,8,4},{0,8,132},{0,8,68},{0,9,232},{16,7,8},
18 {0,8,92},{0,8,28},{0,9,152},{20,7,83},{0,8,124},{0,8,60},{0,9,216},
19 {18,7,23},{0,8,108},{0,8,44},{0,9,184},{0,8,12},{0,8,140},{0,8,76},
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
65 { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7,
[all...]
/linux/drivers/staging/media/ipu3/
H A Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
24 .even = { { 0, 3, 122, 7, 3, 0, 0 },
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
31 { 0, -12, 113, 7, 32, -5, 0 },
[all …]
/linux/lib/crypto/powerpc/
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
87 ld 7,0(4)
89 ld 9,16(4)
93 mulld 22,7,6
[all …]
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
14 # 4. c += d; b ^= c; b <<<= 7
19 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
99 addi 9, 1, 256
100 SAVE_VRS 20, 0, 9
101 SAVE_VRS 21, 16, 9
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
26 # to 9 vectors for multiplications.
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
/linux/include/dt-bindings/memory/
H A Dmediatek,mt6893-memory-port.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
10 #include <dt-bindings/memory/mtk-memory-port.h>
17 * modules dma-address-region larbs-ports
19 * vcodec 4G ~ 8G larb4/5/7
21 * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
35 #define M4U_PORT_L0_OVL_2L_RDMA3 MTK_M4U_DOM_ID(0, 7)
37 #define M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM MTK_M4U_DOM_ID(0, 9)
52 #define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_DOM_ID(1, 7)
54 #define M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM MTK_M4U_DOM_ID(1, 9)
79 #define M4U_PORT_L4_VDEC_VLD_EXT_MDP MTK_M4U_DOM_ID(4, 7)
[all …]
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
22 * modules dma-address-region larbs-ports
24 * vcodec 4G ~ 8G larb4/7
27 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
52 /* LARB 4 -- VDEC */
60 #define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
[all …]
H A Dmt8192-larb-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
18 * modules dma-address-region larbs-ports
20 * vcodec 4G ~ 8G larb4/5/7
21 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
22 * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
44 #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7)
63 #define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
65 #define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9)
76 #define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7)
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/pinctrl-sg2042.h>
12 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
14 #include "sg2042-cpus.dtsi"
18 #address-cells = <2>;
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
16 #include "rzv2h-cpg.h"
108 {7, 16},
110 {9, 20},
246 BUS_MSTOP(5, BIT(9))),
267 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
271 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
299 DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
[all …]
H A Dr9a09g056-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
16 #include "rzv2h-cpg.h"
104 {7, 16},
106 {9, 20},
244 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
248 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
270 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
272 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
[all …]
H A Dr9a09g047-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
198 BUS_MSTOP(5, BIT(9))),
247 DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
251 DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
265 DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
267 DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
268 BUS_MSTOP(11, BIT(7))),
[all …]
/linux/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
17 #include <asm/gpr-num.h>
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
113 /* Register-based PAN access, for save/restore purposes */
[all …]
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7,8,9",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
15 "Counter": "0,1,2,3,4,5,6,7,8,9",
26 "Counter": "0,1,2,3,4,5,6,7,8,9",
36 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 "Counter": "0,1,2,3,4,5,6,7",
54 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 "Counter": "0,1,2,3,4,5,6,7,8,9",
73 "Counter": "0,1,2,3,4,5,6,7",
83 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
H A Dfrontend.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
60 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
70 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
29 RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
40 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
41 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
42 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
43 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
44 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
45 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
46 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
[all …]
/linux/drivers/pinctrl/sunplus/
H A Dsppctl_sp7021.c1 // SPDX-License-Identifier: GPL-2.0
19 D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7),
21 D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7),
23 D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7),
25 D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7),
27 D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7),
29 D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7),
31 D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7),
32 D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3),
33 D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7),
[all …]
/linux/drivers/media/pci/cobalt/
H A Dcobalt-cpld.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include "cobalt-cpld.h"
17 return cobalt_bus_read32(cobalt->bar1, ADRS(offset)); in cpld_read()
22 return cobalt_bus_write32(cobalt->bar1, ADRS(offset), val); in cpld_write()
36 …cobalt_info("CPLD HSMA Clk Osc register (read/write) - Must set wr trigger to load default values\… in cpld_info_ver3()
37 cobalt_info("\t\tRegister #7:\t0x%04x (0x0022)\n", in cpld_info_ver3()
41 cobalt_info("\t\tRegister #9:\t0x%04x (0x00fa)\n", in cpld_info_ver3()
133 { 7, 7, 1 }, { 8, 4, 2 }, { 9, 9, 1 },
135 { 14, 7, 2 }, { 16, 4, 4 }, { 18, 9, 2 },
[all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7,8,9",
66 "Counter": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
84 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
H A Dfrontend.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
60 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
70 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dnvidia,tegra186-hsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
30 - bits 15..8:
33 specified then, 32-bit shared mailbox is used.
34 - bits 7..0:
42 - bits 31..24:
[all …]
/linux/lib/crypto/x86/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * Copyright (C) 2017-2019 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
28 .byte 0, 2, 4, 6, 1, 3, 5, 7, 14, 8, 10, 12, 15, 9, 11, 13
29 .byte 14, 4, 9, 13, 10, 8, 15, 6, 5, 1, 0, 11, 3, 12, 2, 7
30 .byte 11, 12, 5, 15, 8, 0, 2, 13, 9, 10, 3, 7, 4, 14, 6, 1
31 .byte 7, 3, 13, 11, 9, 1, 12, 14, 15, 2, 5, 4, 8, 6, 10, 0
32 .byte 9, 5, 2, 10, 0, 7, 4, 15, 3, 14, 11, 6, 13, 1, 12, 8
33 .byte 2, 6, 0, 8, 12, 10, 11, 3, 1, 4, 7, 15, 9, 13, 5, 14
34 .byte 12, 1, 14, 4, 5, 15, 13, 10, 8, 0, 6, 9, 11, 7, 3, 2
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32mp257.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 #include "pinctrl-stm32.h"
23 STM32_FUNCTION(7, "USART3_TX"),
25 STM32_FUNCTION(9, "TIM5_CH2"),
39 STM32_FUNCTION(7, "USART6_CK"),
41 STM32_FUNCTION(9, "I2C4_SDA"),
56 STM32_FUNCTION(7, "USART1_RX"),
57 STM32_FUNCTION(9, "I3C1_SDA"),
72 STM32_FUNCTION(7, "USART1_TX"),
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8189.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "pinctrl-mtk-mt8189.h"
9 #include "pinctrl-paris.h"
36 PIN_FIELD_BASE(0, 0, 7, 0x00e0, 0x10, 5, 1),
41 PIN_FIELD_BASE(5, 5, 8, 0x00c0, 0x10, 7, 1),
42 PIN_FIELD_BASE(6, 6, 7, 0x00e0, 0x10, 6, 1),
43 PIN_FIELD_BASE(7, 7, 7, 0x00e0, 0x10, 7, 1),
44 PIN_FIELD_BASE(8, 8, 7, 0x00e0, 0x10, 8, 1),
45 PIN_FIELD_BASE(9, 9, 7, 0x00e0, 0x10, 9, 1),
46 PIN_FIELD_BASE(10, 10, 7, 0x00e0, 0x10, 10, 1),
[all …]

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