1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2N CPG driver 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 32 /* Internal Core Clocks */ 33 CLK_PLLCM33_DIV16, 34 CLK_PLLCLN_DIV2, 35 CLK_PLLCLN_DIV8, 36 CLK_PLLDTY_ACPU, 37 CLK_PLLDTY_ACPU_DIV4, 38 39 /* Module Clocks */ 40 MOD_CLK_BASE, 41 }; 42 43 static const struct clk_div_table dtable_1_8[] = { 44 {0, 1}, 45 {1, 2}, 46 {2, 4}, 47 {3, 8}, 48 {0, 0}, 49 }; 50 51 static const struct clk_div_table dtable_2_64[] = { 52 {0, 2}, 53 {1, 4}, 54 {2, 8}, 55 {3, 16}, 56 {4, 64}, 57 {0, 0}, 58 }; 59 60 static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 61 /* External Clock Inputs */ 62 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 63 DEF_INPUT("rtxin", CLK_RTXIN), 64 DEF_INPUT("qextal", CLK_QEXTAL), 65 66 /* PLL Clocks */ 67 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 68 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 69 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 70 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 71 72 /* Internal Core Clocks */ 73 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 74 75 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 76 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 77 78 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 79 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 80 81 /* Core Clocks */ 82 DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 83 DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55, 84 CDDIV1_DIVCTL0, dtable_1_8), 85 DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55, 86 CDDIV1_DIVCTL1, dtable_1_8), 87 DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55, 88 CDDIV1_DIVCTL2, dtable_1_8), 89 DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55, 90 CDDIV1_DIVCTL3, dtable_1_8), 91 DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 92 }; 93 94 static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 95 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 96 BUS_MSTOP(3, BIT(5))), 97 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 98 BUS_MSTOP(3, BIT(14))), 99 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 100 BUS_MSTOP(8, BIT(2))), 101 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 102 BUS_MSTOP(8, BIT(2))), 103 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 104 BUS_MSTOP(8, BIT(2))), 105 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 106 BUS_MSTOP(8, BIT(2))), 107 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 108 BUS_MSTOP(8, BIT(3))), 109 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 110 BUS_MSTOP(8, BIT(3))), 111 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 112 BUS_MSTOP(8, BIT(3))), 113 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 114 BUS_MSTOP(8, BIT(3))), 115 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 116 BUS_MSTOP(8, BIT(4))), 117 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 118 BUS_MSTOP(8, BIT(4))), 119 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 120 BUS_MSTOP(8, BIT(4))), 121 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 122 BUS_MSTOP(8, BIT(4))), 123 }; 124 125 static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 126 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 127 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 128 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 129 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 130 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 131 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 132 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 133 }; 134 135 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = { 136 /* Core Clocks */ 137 .core_clks = r9a09g056_core_clks, 138 .num_core_clks = ARRAY_SIZE(r9a09g056_core_clks), 139 .last_dt_core_clk = LAST_DT_CORE_CLK, 140 .num_total_core_clks = MOD_CLK_BASE, 141 142 /* Module Clocks */ 143 .mod_clks = r9a09g056_mod_clks, 144 .num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks), 145 .num_hw_mod_clks = 25 * 16, 146 147 /* Resets */ 148 .resets = r9a09g056_resets, 149 .num_resets = ARRAY_SIZE(r9a09g056_resets), 150 151 .num_mstop_bits = 192, 152 }; 153