1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G3E CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 32 /* Internal Core Clocks */ 33 CLK_PLLCM33_DIV16, 34 CLK_PLLCLN_DIV16, 35 CLK_PLLDTY_ACPU, 36 CLK_PLLDTY_ACPU_DIV4, 37 38 /* Module Clocks */ 39 MOD_CLK_BASE, 40 }; 41 42 static const struct clk_div_table dtable_1_8[] = { 43 {0, 1}, 44 {1, 2}, 45 {2, 4}, 46 {3, 8}, 47 {0, 0}, 48 }; 49 50 static const struct clk_div_table dtable_2_64[] = { 51 {0, 2}, 52 {1, 4}, 53 {2, 8}, 54 {3, 16}, 55 {4, 64}, 56 {0, 0}, 57 }; 58 59 static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 60 /* External Clock Inputs */ 61 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 62 DEF_INPUT("rtxin", CLK_RTXIN), 63 DEF_INPUT("qextal", CLK_QEXTAL), 64 65 /* PLL Clocks */ 66 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 67 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 68 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 69 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), 70 71 /* Internal Core Clocks */ 72 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 73 74 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 75 76 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 77 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 78 79 /* Core Clocks */ 80 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 81 DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55, 82 CDDIV1_DIVCTL0, dtable_1_8), 83 DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55, 84 CDDIV1_DIVCTL1, dtable_1_8), 85 DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55, 86 CDDIV1_DIVCTL2, dtable_1_8), 87 DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, 88 CDDIV1_DIVCTL3, dtable_1_8), 89 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 90 }; 91 92 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 93 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 94 BUS_MSTOP(3, BIT(5))), 95 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 96 BUS_MSTOP(3, BIT(14))), 97 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 98 BUS_MSTOP(3, BIT(13))), 99 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 100 BUS_MSTOP(1, BIT(1))), 101 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 102 BUS_MSTOP(1, BIT(2))), 103 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 104 BUS_MSTOP(1, BIT(3))), 105 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 106 BUS_MSTOP(1, BIT(4))), 107 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 108 BUS_MSTOP(1, BIT(5))), 109 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 110 BUS_MSTOP(1, BIT(6))), 111 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 112 BUS_MSTOP(1, BIT(7))), 113 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 114 BUS_MSTOP(1, BIT(8))), 115 }; 116 117 static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 118 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 119 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 120 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 121 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 122 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 123 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 124 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 125 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 126 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 127 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 128 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 129 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 130 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 131 }; 132 133 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { 134 /* Core Clocks */ 135 .core_clks = r9a09g047_core_clks, 136 .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks), 137 .last_dt_core_clk = LAST_DT_CORE_CLK, 138 .num_total_core_clks = MOD_CLK_BASE, 139 140 /* Module Clocks */ 141 .mod_clks = r9a09g047_mod_clks, 142 .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks), 143 .num_hw_mod_clks = 28 * 16, 144 145 /* Resets */ 146 .resets = r9a09g047_resets, 147 .num_resets = ARRAY_SIZE(r9a09g047_resets), 148 149 .num_mstop_bits = 208, 150 }; 151