1*1f9e24e4SIan Rogers[ 2*1f9e24e4SIan Rogers { 3*1f9e24e4SIan Rogers "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", 4*1f9e24e4SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 5*1f9e24e4SIan Rogers "EventCode": "0x80", 6*1f9e24e4SIan Rogers "EventName": "ICACHE.ACCESSES", 7*1f9e24e4SIan Rogers "SampleAfterValue": "1000003", 8*1f9e24e4SIan Rogers "UMask": "0x3", 9*1f9e24e4SIan Rogers "Unit": "cpu_atom" 10*1f9e24e4SIan Rogers }, 11*1f9e24e4SIan Rogers { 12*1f9e24e4SIan Rogers "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", 13*1f9e24e4SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 14*1f9e24e4SIan Rogers "EventCode": "0x80", 15*1f9e24e4SIan Rogers "EventName": "ICACHE.MISSES", 16*1f9e24e4SIan Rogers "SampleAfterValue": "1000003", 17*1f9e24e4SIan Rogers "UMask": "0x2", 18*1f9e24e4SIan Rogers "Unit": "cpu_atom" 19*1f9e24e4SIan Rogers }, 20*1f9e24e4SIan Rogers { 21*1f9e24e4SIan Rogers "BriefDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", 22*1f9e24e4SIan Rogers "Counter": "0,1,2,3,4,5,6,7,8,9", 23*1f9e24e4SIan Rogers "EventCode": "0x9c", 24*1f9e24e4SIan Rogers "EventName": "IDQ_BUBBLES.CORE", 25*1f9e24e4SIan Rogers "PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", 26*1f9e24e4SIan Rogers "SampleAfterValue": "1000003", 27*1f9e24e4SIan Rogers "UMask": "0x1", 28*1f9e24e4SIan Rogers "Unit": "cpu_core" 29*1f9e24e4SIan Rogers } 30*1f9e24e4SIan Rogers] 31