Lines Matching +full:7 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
197 BUS_MSTOP(5, BIT(9))),
218 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
222 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
248 DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
252 DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
262 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
264 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
266 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
268 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
270 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
272 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
274 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
276 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
278 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
280 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
282 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
283 BUS_MSTOP(1, BIT(7))),
284 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
286 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
300 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
304 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
317 BUS_MSTOP(7, BIT(7))),
319 BUS_MSTOP(7, BIT(8))),
321 BUS_MSTOP(7, BIT(9))),
323 BUS_MSTOP(7, BIT(10))),
324 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
325 BUS_MSTOP(7, BIT(11))),
328 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
351 BUS_MSTOP(9, BIT(4))),
353 BUS_MSTOP(9, BIT(4))),
355 BUS_MSTOP(9, BIT(4))),
357 BUS_MSTOP(9, BIT(5))),
359 BUS_MSTOP(9, BIT(5))),
360 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
361 BUS_MSTOP(9, BIT(5))),
363 BUS_MSTOP(9, BIT(6))),
364 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
365 BUS_MSTOP(9, BIT(6))),
367 BUS_MSTOP(9, BIT(6))),
369 BUS_MSTOP(9, BIT(7))),
371 BUS_MSTOP(9, BIT(7))),
373 BUS_MSTOP(9, BIT(7))),
374 DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
376 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
378 DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
389 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
390 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
391 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
395 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
396 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
397 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
398 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
399 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
400 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
401 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
402 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
403 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
404 DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
405 DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
406 DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
407 DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
408 DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
410 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
411 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
412 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
413 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
414 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
415 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
416 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
417 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
418 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
419 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
420 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
424 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
426 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
435 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
437 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */