Lines Matching +full:7 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
14 # 4. c += d; b ^= c; b <<<= 7
19 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
99 addi 9, 1, 256
100 SAVE_VRS 20, 0, 9
101 SAVE_VRS 21, 16, 9
102 SAVE_VRS 22, 32, 9
103 SAVE_VRS 23, 48, 9
104 SAVE_VRS 24, 64, 9
105 SAVE_VRS 25, 80, 9
106 SAVE_VRS 26, 96, 9
107 SAVE_VRS 27, 112, 9
108 SAVE_VRS 28, 128, 9
109 SAVE_VRS 29, 144, 9
110 SAVE_VRS 30, 160, 9
111 SAVE_VRS 31, 176, 9
113 SAVE_VSX 14, 192, 9
114 SAVE_VSX 15, 208, 9
115 SAVE_VSX 16, 224, 9
116 SAVE_VSX 17, 240, 9
117 SAVE_VSX 18, 256, 9
118 SAVE_VSX 19, 272, 9
119 SAVE_VSX 20, 288, 9
120 SAVE_VSX 21, 304, 9
121 SAVE_VSX 22, 320, 9
122 SAVE_VSX 23, 336, 9
123 SAVE_VSX 24, 352, 9
124 SAVE_VSX 25, 368, 9
125 SAVE_VSX 26, 384, 9
126 SAVE_VSX 27, 400, 9
127 SAVE_VSX 28, 416, 9
128 SAVE_VSX 29, 432, 9
129 SAVE_VSX 30, 448, 9
130 SAVE_VSX 31, 464, 9
134 addi 9, 1, 256
135 RESTORE_VRS 20, 0, 9
136 RESTORE_VRS 21, 16, 9
137 RESTORE_VRS 22, 32, 9
138 RESTORE_VRS 23, 48, 9
139 RESTORE_VRS 24, 64, 9
140 RESTORE_VRS 25, 80, 9
141 RESTORE_VRS 26, 96, 9
142 RESTORE_VRS 27, 112, 9
143 RESTORE_VRS 28, 128, 9
144 RESTORE_VRS 29, 144, 9
145 RESTORE_VRS 30, 160, 9
146 RESTORE_VRS 31, 176, 9
148 RESTORE_VSX 14, 192, 9
149 RESTORE_VSX 15, 208, 9
150 RESTORE_VSX 16, 224, 9
151 RESTORE_VSX 17, 240, 9
152 RESTORE_VSX 18, 256, 9
153 RESTORE_VSX 19, 272, 9
154 RESTORE_VSX 20, 288, 9
155 RESTORE_VSX 21, 304, 9
156 RESTORE_VSX 22, 320, 9
157 RESTORE_VSX 23, 336, 9
158 RESTORE_VSX 24, 352, 9
159 RESTORE_VSX 25, 368, 9
160 RESTORE_VSX 26, 384, 9
161 RESTORE_VSX 27, 400, 9
162 RESTORE_VSX 28, 416, 9
163 RESTORE_VSX 29, 432, 9
164 RESTORE_VSX 30, 448, 9
165 RESTORE_VSX 31, 464, 9
198 vadduwm 3, 3, 7
214 vadduwm 9, 9, 13
222 vxor 5, 5, 9
224 vxor 7, 7, 11
235 vrlw 7, 7, 25
244 vadduwm 3, 3, 7
262 vadduwm 9, 9, 13
272 vxor 5, 5, 9
274 vxor 7, 7, 11
282 vrlw 7, 7, 28
294 vadduwm 2, 2, 7
314 vadduwm 9, 9, 14
321 vxor 7, 7, 8
322 vxor 4, 4, 9
332 vrlw 7, 7, 25
342 vadduwm 2, 2, 7
364 vadduwm 9, 9, 14
374 vxor 7, 7, 8
375 vxor 4, 4, 9
382 vrlw 7, 7, 28
396 vadduwm 3, 3, 7
402 vadduwm 9, 9, 13
406 vxor 5, 5, 9
408 vxor 7, 7, 11
412 vrlw 7, 7, 21
416 vadduwm 3, 3, 7
422 vadduwm 9, 9, 13
426 vxor 5, 5, 9
428 vxor 7, 7, 11
432 vrlw 7, 7, 23
437 vadduwm 2, 2, 7
446 vadduwm 9, 9, 14
449 vxor 7, 7, 8
450 vxor 4, 4, 9
453 vrlw 7, 7, 21
457 vadduwm 2, 2, 7
466 vadduwm 9, 9, 14
469 vxor 7, 7, 8
470 vxor 4, 4, 9
473 vrlw 7, 7, 23
491 vadduwm \S+0, \S+0, 16-\S
492 vadduwm \S+4, \S+4, 17-\S
493 vadduwm \S+8, \S+8, 18-\S
494 vadduwm \S+12, \S+12, 19-\S
496 vadduwm \S+1, \S+1, 16-\S
497 vadduwm \S+5, \S+5, 17-\S
498 vadduwm \S+9, \S+9, 18-\S
499 vadduwm \S+13, \S+13, 19-\S
501 vadduwm \S+2, \S+2, 16-\S
502 vadduwm \S+6, \S+6, 17-\S
503 vadduwm \S+10, \S+10, 18-\S
504 vadduwm \S+14, \S+14, 19-\S
506 vadduwm \S+3, \S+3, 16-\S
507 vadduwm \S+7, \S+7, 17-\S
508 vadduwm \S+11, \S+11, 18-\S
509 vadduwm \S+15, \S+15, 19-\S
516 add 9, 14, 5
518 lxvw4x 0, 0, 9
519 lxvw4x 1, 17, 9
520 lxvw4x 2, 18, 9
521 lxvw4x 3, 19, 9
522 lxvw4x 4, 20, 9
523 lxvw4x 5, 21, 9
524 lxvw4x 6, 22, 9
525 lxvw4x 7, 23, 9
526 lxvw4x 8, 24, 9
527 lxvw4x 9, 25, 9
528 lxvw4x 10, 26, 9
529 lxvw4x 11, 27, 9
530 lxvw4x 12, 28, 9
531 lxvw4x 13, 29, 9
532 lxvw4x 14, 30, 9
533 lxvw4x 15, 31, 9
542 xxlxor \S+45, \S+45, 7
544 xxlxor \S+38, \S+38, 9
585 # r17 - r31 mainly for Write_256 macro.
620 vspltisw 23, 7
627 sradi 8, 7, 1
664 xxspltw 32+7, 17, 3
666 xxspltw 32+9, 18, 1
705 TP_4x 4, 5, 6, 7
706 TP_4x 8, 9, 10, 11
724 addi 15, 15, -256 # len -=256
731 TP_4x 16+4, 16+5, 16+6, 16+7
732 TP_4x 16+8, 16+9, 16+10, 16+11
742 addi 15, 15, -256 # len +=256
768 vspltisw 23, 7
774 sradi 8, 7, 1
786 vspltw 7, 17, 3
788 vspltw 9, 18, 1
805 TP_4x 4, 5, 6, 7
806 TP_4x 8, 9, 10, 11
812 addi 15, 15, -256 # len += 256