Lines Matching +full:7 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
17 #include <asm/gpr-num.h>
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
113 /* Register-based PAN access, for save/restore purposes */
121 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
126 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
127 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
128 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
129 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
130 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
131 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
132 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
133 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
134 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
136 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
137 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
138 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
140 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
141 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
142 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
144 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
145 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
146 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
148 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
150 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
151 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
152 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
154 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
155 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
156 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
158 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
159 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
160 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
162 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
163 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
164 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
166 #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)
167 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
175 #include "asm/sysreg-defs.h"
188 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
199 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
200 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
201 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
206 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
213 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
215 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
221 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
222 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
228 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
229 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
231 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
247 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
256 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
257 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
258 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
259 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
271 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
322 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
328 #define SYS_PAR_EL1_S BIT(9)
334 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
337 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
338 #define SYS_PAR_EL1_NS BIT(9)
359 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
360 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
362 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
379 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
388 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
396 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
402 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
407 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
408 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
409 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
410 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
411 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
412 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
413 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
414 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
415 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
416 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
417 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
418 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
424 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
442 * n: 0-15
448 * n: 0-15
451 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
452 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
453 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
454 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
483 #define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0)
492 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
494 #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1))
497 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
513 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
553 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
559 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
560 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
563 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
573 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
583 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
587 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
606 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
615 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
619 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
632 #define AT_CRn 7
638 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
639 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
640 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
646 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
647 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
656 #define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/
658 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
659 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
660 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
661 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
662 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
663 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
664 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
665 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
672 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
676 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
682 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
686 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
690 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
691 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
692 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
693 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
694 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
695 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
696 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
697 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
698 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
699 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
700 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
701 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
702 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
703 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
704 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
705 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
706 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
707 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
708 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
709 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
710 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
711 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
712 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
713 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
714 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
715 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
716 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
717 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
718 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
719 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
720 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
721 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
722 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
723 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
724 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
725 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
726 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
750 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
755 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
756 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
757 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
758 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
759 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
760 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
761 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
762 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
763 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
764 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
765 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
766 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
767 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
768 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
769 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
770 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
771 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
772 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
773 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
774 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
775 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
776 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
777 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
778 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
779 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
780 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
781 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
782 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
783 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
784 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
785 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
786 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
787 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
788 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
789 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
790 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
791 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
792 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
795 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
796 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
797 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
798 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
800 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
801 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
802 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
803 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
804 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
805 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
950 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
978 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
998 #define ICH_VMCR_EOIM_SHIFT 9
1001 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1003 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1078 #define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7)
1240 * set mask are set. Other bits are left as-is.