Lines Matching +full:7 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
198 BUS_MSTOP(5, BIT(9))),
247 DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
251 DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
265 DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
267 DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
268 BUS_MSTOP(11, BIT(7))),
269 DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
270 BUS_MSTOP(11, BIT(7))),
271 DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
272 BUS_MSTOP(11, BIT(7))),
273 DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
274 BUS_MSTOP(11, BIT(7))),
275 DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
276 BUS_MSTOP(11, BIT(7))),
277 DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
279 DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
281 DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
283 DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
285 DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
287 DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
288 BUS_MSTOP(11, BIT(9))),
289 DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
290 BUS_MSTOP(11, BIT(9))),
291 DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
292 BUS_MSTOP(11, BIT(9))),
293 DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
294 BUS_MSTOP(11, BIT(9))),
295 DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
296 BUS_MSTOP(11, BIT(9))),
311 DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
315 DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9,
329 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
331 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
333 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
335 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
337 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
339 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
341 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
343 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
345 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
347 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
349 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
350 BUS_MSTOP(1, BIT(7))),
351 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
353 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
355 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
357 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
359 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
373 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
377 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
390 BUS_MSTOP(7, BIT(12))),
392 BUS_MSTOP(7, BIT(14))),
394 BUS_MSTOP(7, BIT(7))),
396 BUS_MSTOP(7, BIT(8))),
398 BUS_MSTOP(7, BIT(9))),
400 BUS_MSTOP(7, BIT(10))),
401 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
402 BUS_MSTOP(7, BIT(11))),
405 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
428 BUS_MSTOP(9, BIT(4))),
430 BUS_MSTOP(9, BIT(4))),
432 BUS_MSTOP(9, BIT(4))),
433 DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
435 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
437 DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
450 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
451 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
452 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
453 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
457 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
458 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
459 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
466 DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
468 DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */
475 DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */
476 DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */
477 DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
478 DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
479 DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
480 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
481 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
482 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
483 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
484 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
485 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
486 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
487 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
488 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
489 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
490 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
496 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
498 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
508 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
512 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */