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Searched refs:mt76_set (Results 1 – 25 of 52) sorted by relevance

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/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dpci_init.c23 mt76_set(dev, MT_PBF_SYS_CTRL, val); in mt76x2_mac_pbf_init()
55 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); in mt76x2_fixup_xtal()
101 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); in mt76x2_mac_reset()
144 mt76_set(dev, 0x10130, BIT(0) | BIT(16)); in mt76x2_power_on_rf_patch()
148 mt76_set(dev, 0x1001c, 0x30); in mt76x2_power_on_rf_patch()
153 mt76_set(dev, 0x10130, BIT(17)); in mt76x2_power_on_rf_patch()
159 mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); in mt76x2_power_on_rf_patch()
168 mt76_set(dev, 0x10130, BIT(0) << shift); in mt76x2_power_on_rf()
172 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift); in mt76x2_power_on_rf()
181 mt76_set(dev, 0x530, 0xf); in mt76x2_power_on_rf()
[all …]
H A Dusb_init.c30 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); in mt76x2u_power_on_rf_patch()
34 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30); in mt76x2u_power_on_rf_patch()
39 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); in mt76x2u_power_on_rf_patch()
45 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); in mt76x2u_power_on_rf_patch()
54 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); in mt76x2u_power_on_rf()
58 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); in mt76x2u_power_on_rf()
67 mt76_set(dev, 0x530, 0xf); in mt76x2u_power_on_rf()
75 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), in mt76x2u_power_on()
90 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24); in mt76x2u_power_on()
97 mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0)); in mt76x2u_power_on()
H A Dusb_mac.c34 mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL); in mt76x2u_mac_fixup_xtal()
87 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); in mt76x2u_mac_reset()
143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
H A Dmac.c37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
H A Dusb_phy.c145 mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); in mt76x2u_phy_set_channel()
167 mt76_set(dev, MT_BBP(TXO, 4), BIT(25)); in mt76x2u_phy_set_channel()
168 mt76_set(dev, MT_BBP(RXO, 13), BIT(8)); in mt76x2u_phy_set_channel()
H A Dpci_phy.c104 mt76_set(dev, MT_BBP(IBI, 9), BIT(11)); in mt76x2_phy_set_antenna()
105 mt76_set(dev, MT_BBP(TXBE, 5), 3); in mt76x2_phy_set_antenna()
210 mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); in mt76x2_phy_set_channel()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Ddma.c79 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + ofs, WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE); in __mt7996_dma_prefetch()
101 mt76_set(dev, MT_WFDMA0_RST, in mt7996_dma_disable()
110 mt76_set(dev, MT_WFDMA0_RST + hif1_ofs, in mt7996_dma_disable()
144 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt7996_dma_start()
151 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, in mt7996_dma_start()
206 mt76_set(dev, MT_WFDMA0_BUSY_ENA, in mt7996_dma_enable()
212 mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs, in mt7996_dma_enable()
221 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0, in mt7996_dma_enable()
226 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1, in mt7996_dma_enable()
231 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, in mt7996_dma_enable()
[all …]
H A Dcoredump.c157 mt76_set(dev, MT_MCU_WM_EXCP_PC_CTRL, BIT(0)); in mt7996_coredump_fw_stack()
158 mt76_set(dev, MT_MCU_WM_EXCP_LR_CTRL, BIT(0)); in mt7996_coredump_fw_stack()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Ddma.c184 mt76_set(dev, MT_WFDMA0_RST, in mt7915_dma_disable()
193 mt76_set(dev, MT_WFDMA1_RST, in mt7915_dma_disable()
203 mt76_set(dev, MT_WFDMA0_RST + hif1_ofs, in mt7915_dma_disable()
212 mt76_set(dev, MT_WFDMA1_RST + hif1_ofs, in mt7915_dma_disable()
264 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt7915_dma_start()
271 mt76_set(dev, MT_WFDMA1_GLO_CFG, in mt7915_dma_start()
278 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, in mt7915_dma_start()
285 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, in mt7915_dma_start()
291 mt76_set(dev, MT_WFDMA_HOST_CONFIG, in mt7915_dma_start()
376 mt76_set(dev, MT_WFDMA0_BUSY_ENA, in mt7915_dma_enable()
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_dma.c122 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt792x_dma_enable()
130 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt792x_dma_enable()
133 mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT); in mt792x_dma_enable()
142 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); in mt792x_dma_enable()
246 mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS); in mt792x_dma_disable()
254 mt76_set(dev, MT_WFDMA0_RST, in mt792x_dma_disable()
283 mt76_set(dev, MT_WFDMA0_RST, in mt792x_dma_cleanup()
338 mt76_set(dev, addr, WFSYS_SW_RST_B); in mt792x_wfsys_reset()
H A Dmt792x_mac.c53 mt76_set(dev, MT_ARB_SCR(0), in mt792x_mac_set_timeing()
214 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); in mt792x_mac_reset_counters()
215 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); in mt792x_mac_reset_counters()
266 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); in mt792x_update_channel()
295 mt76_set(dev, MT_TMAC_CTCR0(band), in mt792x_mac_init_band()
299 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(band), MT_WF_RMAC_MIB_RXTIME_EN); in mt792x_mac_init_band()
300 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band), MT_WF_RMAC_MIB_RXTIME_EN); in mt792x_mac_init_band()
303 mt76_set(dev, MT_MIB_SCR1(band), MT_MIB_TXDUR_EN); in mt792x_mac_init_band()
304 mt76_set(dev, MT_MIB_SCR1(band), MT_MIB_RXDUR_EN); in mt792x_mac_init_band()
H A Dmt792x_usb.c165 mt76_set(dev, MT_UWFDMA0_GLO_CFG, in mt792xu_wfdma_init()
175 mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS); in mt792xu_wfdma_init()
177 mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT); in mt792xu_wfdma_init()
187 mt76_set(dev, MT_WFDMA_HOST_CONFIG, in mt792xu_dma_rx_evt_ep4()
189 mt76_set(dev, MT_UWFDMA0_GLO_CFG, MT_WFDMA0_GLO_CFG_RX_DMA_EN); in mt792xu_dma_rx_evt_ep4()
219 mt76_set(dev, MT_UDMA_WLCFG_0, in mt792xu_dma_init()
H A Dmt76x02_phy.c41 mt76_set(dev, MT_BBP(TXBE, 5), 0x3); in mt76x02_phy_set_txdac()
155 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G); in mt76x02_phy_set_band()
160 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G); in mt76x02_phy_set_band()
H A Dmt76x02_mmio.c29 mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff); in mt76x02_pre_tbtt_tasklet()
312 mt76_set(dev, MT_WPDMA_GLO_CFG, val); in mt76x02_dma_enable()
465 mt76_set(dev, 0x734, 0x3); in mt76x02_watchdog_reset()
483 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x02_watchdog_reset()
486 mt76_set(dev, MT_BEACON_TIME_CFG, in mt76x02_watchdog_reset()
H A Dmt76x02_beacon.c91 mt76_set(dev, MT_BEACON_TIME_CFG, in mt76x02_mac_set_beacon_enable()
212 mt76_set(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_SYNC_MODE); in mt76x02_init_beacon_config()
H A Dmt76x02_mac.c247 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); in mt76x02_mac_set_short_preamble()
1069 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); in mt76x02_check_mac_err()
1083 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); in mt76x02_edcca_tx_enable()
1084 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); in mt76x02_edcca_tx_enable()
1112 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x02_edcca_init()
1115 mt76_set(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); in mt76x02_edcca_init()
1117 mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); in mt76x02_edcca_init()
1121 mt76_set(dev, MT_TXOP_HLDR_ET, in mt76x02_edcca_init()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dbeacon.c174 mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCAST_PRIO); in mt7603_beacon_set_timer()
178 mt76_set(dev, MT_HW_INT_MASK(3), in mt7603_beacon_set_timer()
181 mt76_set(dev, MT_WF_ARB_BCN_START, in mt7603_beacon_set_timer()
188 mt76_set(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN); in mt7603_beacon_set_timer()
H A Dmac.c26 mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask)); in mt76_stop_tx_ac()
32 mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask)); in mt76_start_tx_ac()
63 mt76_set(dev, MT_ARB_SCR, in mt7603_mac_set_timing()
147 mt76_set(dev, addr + 0 * 4, w0); in mt7603_wtbl_init()
148 mt76_set(dev, addr + 1 * 4, w1); in mt7603_wtbl_init()
149 mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL); in mt7603_wtbl_init()
262 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_set_ps()
300 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_clear()
845 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */ in mt7603_wtbl_set_rates()
1333 mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); in mt7603_pse_reset()
[all …]
H A Dinit.c110 mt76_set(dev, MT_SCH_4, BIT(6)); in mt7603_dma_sched_init()
180 mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT); in mt7603_mac_init()
185 mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE); in mt7603_mac_init()
191 mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS); in mt7603_mac_init()
194 mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11)); in mt7603_mac_init()
197 mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN); in mt7603_mac_init()
258 mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE); in mt7603_mac_init()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Ddma.c204 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_start()
246 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
254 mt76_set(dev, 0x7158, BIT(16)); in mt7615_dma_init()
313 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); in mt7615_dma_cleanup()
H A Dinit.c74 mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(0), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN); in mt7615_phy_init()
75 mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(1), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN); in mt7615_phy_init()
89 mt76_set(dev, MT_CFG_CCR, val); in mt7615_init_mac_chain()
170 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_EN); in mt7615_mac_init()
171 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_EN); in mt7615_mac_init()
179 mt76_set(dev, MT_WF_MIB_SCR0, MT_MIB_SCR0_AGG_CNT_RANGE_EN); in mt7615_mac_init()
H A Dmac.c136 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); in mt7615_mac_reset_counters()
137 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); in mt7615_mac_reset_counters()
164 mt76_set(dev, MT_ARB_SCR, in mt7615_mac_set_timing()
172 mt76_set(dev, MT_ARB_SCR, in mt7615_mac_set_timing()
1189 mt76_set(dev, addr, MT_WTBL_W3_RTS); in mt7615_mac_enable_rtscts()
1755 mt76_set(dev, reg, mask); in mt7615_mac_set_scs()
1757 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); in mt7615_mac_set_scs()
1758 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); in mt7615_mac_set_scs()
1785 mt76_set(dev, rxtd, BIT(18) | BIT(29)); in mt7615_mac_enable_nf()
1786 mt76_set(dev, reg, 0x5 << 12); in mt7615_mac_enable_nf()
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dinit.c90 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); in mt7921_mac_init()
92 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_RX_HDR_TRANS_EN); in mt7921_mac_init()
H A Dusb.c70 mt76_set(dev, MT_UDMA_TX_QSEL, MT_FW_DL_EN); in mt7921u_mcu_init()
113 mt76_set(dev, MT_UDMA_TX_QSEL, MT_FW_DL_EN); in mt7921u_mac_reset()
/freebsd/sys/contrib/dev/mediatek/mt76/mt76x0/
H A Dpci.c123 mt76_set(dev, MT_XO_CTRL7, 0xc03); in mt76x0e_init_hardware()
127 mt76_set(dev, MT_MAX_LEN_CFG, BIT(13)); in mt76x0e_init_hardware()

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