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Searched refs:addReg (Results 1 – 25 of 311) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp164 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
165 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
166 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
170 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
171 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
172 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
198 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
199 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
200 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
207 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
[all …]
H A DAVRFrameLowering.cpp71 .addReg(STI.getTmpRegister(), RegState::Kill) in emitPrologue()
78 .addReg(STI.getTmpRegister(), RegState::Kill) in emitPrologue()
82 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
85 .addReg(STI.getZeroRegister(), RegState::Define) in emitPrologue()
86 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
87 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
109 .addReg(AVR::SP) in emitPrologue()
126 .addReg(AVR::R29R28, RegState::Kill) in emitPrologue()
134 .addReg(AVR::R29R28) in emitPrologue()
157 .addReg(ST in restoreStatusRegister()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp164 .addReg(AddrReg) in doAtomicBinOpExpansion()
171 .addReg(IncrReg) in doAtomicBinOpExpansion()
172 .addReg(LoongArch::R0); in doAtomicBinOpExpansion()
176 .addReg(DestReg) in doAtomicBinOpExpansion()
177 .addReg(IncrReg); in doAtomicBinOpExpansion()
179 .addReg(ScratchReg) in doAtomicBinOpExpansion()
180 .addReg(LoongArch::R0); in doAtomicBinOpExpansion()
184 .addReg(DestReg) in doAtomicBinOpExpansion()
185 .addReg(IncrReg); in doAtomicBinOpExpansion()
189 .addReg(DestRe in doAtomicBinOpExpansion()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
147 .addReg(Scratch) in expandAtomicCmpSwapSubword()
148 .addReg(Mask); in expandAtomicCmpSwapSubword()
150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB); in expandAtomicCmpSwapSubword()
158 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
159 .addReg(Mask2); in expandAtomicCmpSwapSubword()
161 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
162 .addReg(ShiftNewVal); in expandAtomicCmpSwapSubword()
164 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
165 .addReg(Ptr) in expandAtomicCmpSwapSubword()
[all …]
H A DMipsFastISel.cpp217 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
222 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
365 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
368 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
377 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
400 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
418 .addReg(MFI->getGlobalBaseReg(*MF)) in materializeGV()
424 .addReg(DestReg) in materializeGV()
[all …]
H A DMipsBranchExpansion.cpp351 MIB.addReg(MO.getReg()); in replaceBranch()
400 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
470 .addReg(Mips::SP) in expandToLongBranch()
473 .addReg(Mips::RA) in expandToLongBranch()
474 .addReg(Mips::SP) in expandToLongBranch()
501 .addReg(Mips::AT) in expandToLongBranch()
516 .addReg(Mips::RA) in expandToLongBranch()
517 .addReg(Mips::AT); in expandToLongBranch()
519 .addReg(Mips::SP) in expandToLongBranch()
531 .addReg(Mips::SP) in expandToLongBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
171 .addReg(IncrLo) in expandAtomicRMW128()
172 .addReg(OldLo); in expandAtomicRMW128()
[all …]
H A DPPCFrameLowering.cpp798 MIB.addReg(MustSaveCRs[0], RegState::Kill); in emitPrologue()
803 MIB.addReg(CRfield, RegState::ImplicitKill); in emitPrologue()
812 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
814 .addReg(SPReg); in emitPrologue()
826 .addReg(FPReg) in emitPrologue()
828 .addReg(SPReg); in emitPrologue()
831 .addReg(PPC::R30) in emitPrologue()
833 .addReg(SPReg); in emitPrologue()
836 .addReg(BPReg) in emitPrologue()
838 .addReg(SPReg); in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp278 .addReg(AddrReg); in insertMaskedMerge()
284 .addReg(DestReg) in insertMaskedMerge()
285 .addReg(IncrReg); in insertMaskedMerge()
287 .addReg(ScratchReg) in insertMaskedMerge()
292 .addReg(AddrReg) in insertMaskedMerge()
293 .addReg(ScratchReg); in insertMaskedMerge()
295 .addReg(ScratchReg) in insertMaskedMerge()
296 .addReg(RISCV::X0)
312 .addReg(OldValReg) in doMaskedAtomicBinOpExpansion()
313 .addReg(NewValRe in doMaskedAtomicBinOpExpansion()
[all...]
H A DRISCVAsmPrinter.cpp174 .addReg(RISCV::X1) in LowerPATCHPOINT()
175 .addReg(RISCV::X1) in LowerPATCHPOINT()
220 .addReg(RISCV::X1) in LowerSTATEPOINT()
226 .addReg(RISCV::X1) in LowerSTATEPOINT()
561 .addReg(ScratchRegs[0]) in LowerKCFI_CHECK()
562 .addReg(RISCV::X0) in LowerKCFI_CHECK()
577 .addReg(ScratchRegs[0]) in LowerKCFI_CHECK()
578 .addReg(AddrReg) in LowerKCFI_CHECK()
589 MCInstBuilder(RISCV::LUI).addReg(ScratchRegs[1]).addImm(Hi20)); in LowerKCFI_CHECK()
596 .addReg(ScratchRegs[1]) in LowerKCFI_CHECK()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp412 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
413 .addReg(AArch64::XZR) in LowerPATCHABLE_EVENT_CALL()
414 .addReg(MI.getOperand(0).getReg()) in LowerPATCHABLE_EVENT_CALL()
417 .addReg(AArch64::X1) in LowerPATCHABLE_EVENT_CALL()
418 .addReg(AArch64::XZR) in LowerPATCHABLE_EVENT_CALL()
419 .addReg(MI.getOperand(1).getReg()) in LowerPATCHABLE_EVENT_CALL()
431 .addReg(AArch64::SP) in LowerPATCHABLE_EVENT_CALL()
432 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
433 .addReg(AArch64::X1) in LowerPATCHABLE_EVENT_CALL()
434 .addReg(AArch64::SP) in LowerPATCHABLE_EVENT_CALL()
[all …]
H A DAArch64SIMDInstrOpt.cpp451 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
455 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
456 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
457 .addReg(DupDest, Src2IsKill); in optimizeVectElement()
463 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
467 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
468 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
567 .addReg(StReg[0]) in optimizeLdStInterleave()
568 .addReg(StReg[1]); in optimizeLdStInterleave()
570 .addReg(StRe in optimizeLdStInterleave()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp182 .addReg(TIP.first) in runOnMachineFunction()
185 .addReg(0)); in runOnMachineFunction()
1064 .addReg(0)); in emitJumpTableInsts()
1470 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1474 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1486 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1490 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1497 .addReg(ARM::LR) in emitInstruction()
1498 .addReg(ARM::PC) in emitInstruction()
1501 .addReg(0) in emitInstruction()
[all …]
H A DARMExpandPseudoInsts.cpp590 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
594 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
596 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
598 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
600 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
659 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
720 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
722 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
724 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
726 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp43 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
47 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
57 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
61 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
62 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
70 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
71 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
72 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
123 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
H A DSystemZFrameLowering.cpp308 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR()
340 MIB.addReg(SystemZ::R15D).addImm(SpillGPRs.GPROffset); in spillCalleeSavedRegisters()
411 MIB.addReg(RestoreGPRs.LowGPR, RegState::Define); in restoreCalleeSavedRegisters()
412 MIB.addReg(RestoreGPRs.HighGPR, RegState::Define); in restoreCalleeSavedRegisters()
415 MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D); in restoreCalleeSavedRegisters()
423 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
496 .addReg(Reg).addImm(ThisVal); in emitIncrement()
625 .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D); in emitPrologue()
630 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D) in emitPrologue()
631 .addImm(getBackchainOffset(MF)).addReg(0); in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
177 MIB.addReg(AM.Base.Reg); in addFullAddress()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
189 return MIB.addReg(0); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp153 .addReg(VE::SX11) in emitPrologueInsns()
156 .addReg(VE::SX9); in emitPrologueInsns()
158 .addReg(VE::SX11) in emitPrologueInsns()
161 .addReg(VE::SX10); in emitPrologueInsns()
165 .addReg(VE::SX11) in emitPrologueInsns()
168 .addReg(VE::SX15); in emitPrologueInsns()
170 .addReg(VE::SX11) in emitPrologueInsns()
173 .addReg(VE::SX16); in emitPrologueInsns()
177 .addReg(VE::SX11) in emitPrologueInsns()
180 .addReg(VE::SX17); in emitPrologueInsns()
[all …]
H A DVERegisterInfo.cpp214 build(VE::ANDrm, clobber).addReg(clobber).addImm(M0(32)); in prepareReplaceFI()
216 .addReg(clobber) in prepareReplaceFI()
217 .addReg(FrameReg) in prepareReplaceFI()
248 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg); in processSTQ()
269 build(VE::LDrii, DestLoReg).addReg(FrameReg).addImm(0).addImm(0); in processLDQ()
302 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i); in processSTVM()
304 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM()
309 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
341 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM()
352 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp71 .addReg(FrameReg) in InsertFPImmInst()
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
78 .addReg(FrameReg) in InsertFPImmInst()
84 .addReg(FrameReg) in InsertFPImmInst()
108 .addReg(FrameReg) in InsertFPConstInst()
109 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
115 .addReg(FrameReg) in InsertFPConstInst()
116 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
121 .addReg(FrameReg) in InsertFPConstInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp250 .addReg(DstReg) in movImm()
266 .addReg(DstReg) in movImm()
271 .addReg(DstReg) in movImm()
279 .addReg(DstReg) in movImm()
284 .addReg(DstReg) in movImm()
288 .addReg(DstReg) in movImm()
293 .addReg(DstReg) in movImm()
301 .addReg(DstReg) in movImm()
306 .addReg(DstReg) in movImm()
310 .addReg(DstReg) in movImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp647 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
650 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
658 .addReg(P.first); in splitMemRef()
660 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
662 .addReg(P.second); in splitMemRef()
674 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
740 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
748 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
766 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp197 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
222 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
232 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
261 .addReg(ImpDefReg) in selectZExt()
262 .addReg(SrcReg) in selectZExt()
267 .addReg(NewDefReg) in selectZExt()
331 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
348 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp169 .addReg(SrcReg); in selectCOPY()
175 .addReg(MaskedReg); in selectCOPY()
255 .addReg(Reg, 0, ComposedSubIdx); in getSubOperand64()
393 .addReg(CarryReg, RegState::Kill) in selectG_ADD_SUB()
401 .addReg(DstLo) in selectG_ADD_SUB()
403 .addReg(DstHi) in selectG_ADD_SUB()
441 .addReg(I.getOperand(4).getReg()); in selectG_UADDO_USUBO_UADDE_USUBE()
455 .addReg(AMDGPU::SCC); in selectG_UADDO_USUBO_UADDE_USUBE()
532 .addReg(SrcReg, 0, SubReg); in selectG_EXTRACT()
561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
[all …]

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