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Searched refs:addReg (Results 1 – 25 of 315) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp162 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
163 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
164 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
168 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
169 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
170 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
196 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
197 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
198 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
205 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
[all …]
H A DAVRFrameLowering.cpp70 .addReg(STI.getTmpRegister(), RegState::Kill) in emitPrologue()
77 .addReg(STI.getTmpRegister(), RegState::Kill) in emitPrologue()
81 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
84 .addReg(STI.getZeroRegister(), RegState::Define) in emitPrologue()
85 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
86 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
108 .addReg(AVR::SP) in emitPrologue()
125 .addReg(AVR::R29R28, RegState::Kill) in emitPrologue()
133 .addReg(AVR::R29R28) in emitPrologue()
156 .addReg(STI.getTmpRegister(), RegState::Kill); in restoreStatusRegister()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp144 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
146 .addReg(Scratch) in expandAtomicCmpSwapSubword()
147 .addReg(Mask); in expandAtomicCmpSwapSubword()
149 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB); in expandAtomicCmpSwapSubword()
157 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
158 .addReg(Mask2); in expandAtomicCmpSwapSubword()
160 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
161 .addReg(ShiftNewVal); in expandAtomicCmpSwapSubword()
163 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
164 .addReg(Ptr) in expandAtomicCmpSwapSubword()
[all …]
H A DMipsFastISel.cpp215 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
220 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
326 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
363 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
366 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
375 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
390 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
398 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
416 .addReg(MFI->getGlobalBaseReg(*MF)) in materializeGV()
422 .addReg(DestReg) in materializeGV()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp180 .addReg(AddrReg) in doAtomicBinOpExpansion()
187 .addReg(IncrReg) in doAtomicBinOpExpansion()
188 .addReg(LoongArch::R0); in doAtomicBinOpExpansion()
192 .addReg(DestReg) in doAtomicBinOpExpansion()
193 .addReg(IncrReg); in doAtomicBinOpExpansion()
195 .addReg(ScratchReg) in doAtomicBinOpExpansion()
196 .addReg(LoongArch::R0); in doAtomicBinOpExpansion()
200 .addReg(DestReg) in doAtomicBinOpExpansion()
201 .addReg(IncrReg); in doAtomicBinOpExpansion()
205 .addReg(DestReg) in doAtomicBinOpExpansion()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp56 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
57 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
58 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
62 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
159 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
168 .addReg(IncrLo) in expandAtomicRMW128()
169 .addReg(OldLo); in expandAtomicRMW128()
[all …]
H A DPPCFrameLowering.cpp798 MIB.addReg(MustSaveCRs[0], RegState::Kill); in emitPrologue()
803 MIB.addReg(CRfield, RegState::ImplicitKill); in emitPrologue()
812 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
814 .addReg(SPReg); in emitPrologue()
826 .addReg(FPReg) in emitPrologue()
828 .addReg(SPReg); in emitPrologue()
831 .addReg(PPC::R30) in emitPrologue()
833 .addReg(SPReg); in emitPrologue()
836 .addReg(BPReg) in emitPrologue()
838 .addReg(SPReg); in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp185 .addReg(TIP.first) in runOnMachineFunction()
188 .addReg(0)); in runOnMachineFunction()
1071 .addReg(0)); in emitJumpTableInsts()
1498 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1502 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1514 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1518 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1525 .addReg(ARM::LR) in emitInstruction()
1526 .addReg(ARM::PC) in emitInstruction()
1529 .addReg(0) in emitInstruction()
[all …]
H A DARMExpandPseudoInsts.cpp589 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
593 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
595 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
597 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
599 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
658 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
719 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
721 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
723 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
725 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp276 .addReg(AddrReg); in doAtomicBinOpExpansion()
282 .addReg(DestReg) in doAtomicBinOpExpansion()
283 .addReg(IncrReg); in doAtomicBinOpExpansion()
285 .addReg(ScratchReg) in doAtomicBinOpExpansion()
290 .addReg(AddrReg) in doAtomicBinOpExpansion()
291 .addReg(ScratchReg); in doAtomicBinOpExpansion()
293 .addReg(ScratchReg) in doAtomicBinOpExpansion()
294 .addReg(RISCV::X0) in doAtomicBinOpExpansion()
310 .addReg(OldValReg) in insertMaskedMerge()
311 .addReg(NewValReg); in insertMaskedMerge()
[all …]
H A DRISCVAsmPrinter.cpp193 .addReg(RISCV::X1) in LowerPATCHPOINT()
194 .addReg(RISCV::X1) in LowerPATCHPOINT()
239 .addReg(RISCV::X1) in LowerSTATEPOINT()
245 .addReg(RISCV::X1) in LowerSTATEPOINT()
532 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addExpr(TargetExpr)); in emitSled()
537 .addReg(RISCV::X0) in emitSled()
538 .addReg(RISCV::X0) in emitSled()
667 .addReg(ScratchRegs[0]) in LowerKCFI_CHECK()
668 .addReg(RISCV::X0) in LowerKCFI_CHECK()
683 .addReg(ScratchRegs[0]) in LowerKCFI_CHECK()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp46 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
51 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
60 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
64 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
65 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
73 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
74 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
75 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
124 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
H A DSystemZFrameLowering.cpp310 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR()
342 MIB.addReg(SystemZ::R15D).addImm(SpillGPRs.GPROffset); in spillCalleeSavedRegisters()
413 MIB.addReg(RestoreGPRs.LowGPR, RegState::Define); in restoreCalleeSavedRegisters()
414 MIB.addReg(RestoreGPRs.HighGPR, RegState::Define); in restoreCalleeSavedRegisters()
417 MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D); in restoreCalleeSavedRegisters()
425 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
498 .addReg(Reg).addImm(ThisVal); in emitIncrement()
570 .addReg(SystemZ::R14D) in emitPrologue()
571 .addReg(SystemZ::R15D) in emitPrologue()
573 .addReg(0); in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp545 .addReg(AArch64::SP) in LowerPATCHABLE_EVENT_CALL()
546 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
547 .addReg(AArch64::X1) in LowerPATCHABLE_EVENT_CALL()
548 .addReg(AArch64::SP) in LowerPATCHABLE_EVENT_CALL()
551 .addReg(AArch64::X2) in LowerPATCHABLE_EVENT_CALL()
552 .addReg(AArch64::SP) in LowerPATCHABLE_EVENT_CALL()
559 .addReg(AArch64::X2) in LowerPATCHABLE_EVENT_CALL()
560 .addReg(AArch64::SP) in LowerPATCHABLE_EVENT_CALL()
564 .addReg(AArch64::SP) in LowerPATCHABLE_EVENT_CALL()
565 .addReg(AArch64::X0) in LowerPATCHABLE_EVENT_CALL()
[all …]
H A DAArch64SIMDInstrOpt.cpp449 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
453 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
454 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
455 .addReg(DupDest, Src2IsKill); in optimizeVectElement()
461 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
465 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
466 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
565 .addReg(StReg[0]) in optimizeLdStInterleave()
566 .addReg(StReg[1]); in optimizeLdStInterleave()
568 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
[all …]
H A DAArch64ExpandPseudoInsts.cpp157 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
164 .addReg(DstReg, RegState::Define | in expandMOVImm()
167 .addReg(DstReg) in expandMOVImm()
177 .addReg(DstReg, RegState::Define | in expandMOVImm()
180 .addReg(DstReg) in expandMOVImm()
181 .addReg(DstReg) in expandMOVImm()
189 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
196 .addReg(DstReg, RegState::Define | in expandMOVImm()
199 .addReg(DstReg) in expandMOVImm()
209 .addReg(DstReg, RegState::Define | in expandMOVImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h121 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
138 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
143 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
153 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
161 return MIB.addReg(Reg1, getKillRegState(isKill1), SubReg1) in addRegReg()
163 .addReg(Reg2, getKillRegState(isKill2), SubReg2) in addRegReg()
165 .addReg(0); in addRegReg()
174 MIB.addReg(AM.Base.Reg); in addFullAddress()
180 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
186 return MIB.addReg(0); in addFullAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp38 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
41 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
80 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
83 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) in expandMEMCPY()
94 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
96 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
101 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
103 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
108 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
110 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp150 .addReg(VE::SX11) in emitPrologueInsns()
153 .addReg(VE::SX9); in emitPrologueInsns()
155 .addReg(VE::SX11) in emitPrologueInsns()
158 .addReg(VE::SX10); in emitPrologueInsns()
162 .addReg(VE::SX11) in emitPrologueInsns()
165 .addReg(VE::SX15); in emitPrologueInsns()
167 .addReg(VE::SX11) in emitPrologueInsns()
170 .addReg(VE::SX16); in emitPrologueInsns()
174 .addReg(VE::SX11) in emitPrologueInsns()
177 .addReg(VE::SX17); in emitPrologueInsns()
[all …]
H A DVERegisterInfo.cpp210 build(VE::ANDrm, clobber).addReg(clobber).addImm(M0(32)); in prepareReplaceFI()
212 .addReg(clobber) in prepareReplaceFI()
213 .addReg(FrameReg) in prepareReplaceFI()
244 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg); in processSTQ()
265 build(VE::LDrii, DestLoReg).addReg(FrameReg).addImm(0).addImm(0); in processLDQ()
298 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i); in processSTVM()
300 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM()
305 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
337 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM()
348 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp66 .addReg(FrameReg) in InsertFPImmInst()
72 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
73 .addReg(FrameReg) in InsertFPImmInst()
79 .addReg(FrameReg) in InsertFPImmInst()
103 .addReg(FrameReg) in InsertFPConstInst()
104 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
109 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
110 .addReg(FrameReg) in InsertFPConstInst()
111 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
116 .addReg(FrameReg) in InsertFPConstInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp69 .addReg(SP) in emitPrologue()
76 .addReg(SP) in emitPrologue()
80 .addReg(SP) in emitPrologue()
81 .addReg(TmpReg); in emitPrologue()
82 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::MOVSP), SP).addReg(TmpReg); in emitPrologue()
96 .addReg(RegMisAlign, RegState::Define) in emitPrologue()
97 .addReg(FP) in emitPrologue()
98 .addReg(RegMisAlign); in emitPrologue()
100 .addReg(Reg) in emitPrologue()
101 .addReg(RegMisAlign); in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp250 .addReg(DstReg) in movImm()
266 .addReg(DstReg) in movImm()
271 .addReg(DstReg) in movImm()
279 .addReg(DstReg) in movImm()
284 .addReg(DstReg) in movImm()
288 .addReg(DstReg) in movImm()
293 .addReg(DstReg) in movImm()
301 .addReg(DstReg) in movImm()
306 .addReg(DstReg) in movImm()
310 .addReg(DstReg) in movImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp641 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
644 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
650 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
652 .addReg(P.first); in splitMemRef()
654 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
656 .addReg(P.second); in splitMemRef()
668 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
734 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
742 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
760 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp197 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
222 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
232 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
261 .addReg(ImpDefReg) in selectZExt()
262 .addReg(SrcReg) in selectZExt()
267 .addReg(NewDefReg) in selectZExt()
331 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
348 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
[all …]

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