Lines Matching refs:addReg
169 .addReg(SrcReg); in selectCOPY()
175 .addReg(MaskedReg); in selectCOPY()
255 .addReg(Reg, 0, ComposedSubIdx); in getSubOperand64()
393 .addReg(CarryReg, RegState::Kill) in selectG_ADD_SUB()
401 .addReg(DstLo) in selectG_ADD_SUB()
403 .addReg(DstHi) in selectG_ADD_SUB()
441 .addReg(I.getOperand(4).getReg()); in selectG_UADDO_USUBO_UADDE_USUBE()
455 .addReg(AMDGPU::SCC); in selectG_UADDO_USUBO_UADDE_USUBE()
532 .addReg(SrcReg, 0, SubReg); in selectG_EXTRACT()
561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
605 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
704 .addReg(Src0); in selectG_BUILD_VECTOR()
709 .addReg(Src1) in selectG_BUILD_VECTOR()
711 .addReg(TmpReg); in selectG_BUILD_VECTOR()
754 .addReg(ShiftSrc0) in selectG_BUILD_VECTOR()
837 .addReg(Src0Reg) in selectG_INSERT()
838 .addReg(Src1Reg) in selectG_INSERT()
862 .addReg(SrcReg) in selectG_SBFX_UBFX()
863 .addReg(OffsetReg) in selectG_SBFX_UBFX()
864 .addReg(WidthReg); in selectG_SBFX_UBFX()
893 .addReg(M0Val); in selectInterpP1F16()
901 .addReg(Src0) // $src0 in selectInterpP1F16()
905 .addReg(InterpMov) // $src2 - 2 f16 values selected by high in selectInterpP1F16()
938 MIB.addReg(Val); in selectWritelane()
950 MIB.addReg(LaneSelect); in selectWritelane()
952 MIB.addReg(Val); in selectWritelane()
960 .addReg(LaneSelect); in selectWritelane()
961 MIB.addReg(AMDGPU::M0); in selectWritelane()
965 MIB.addReg(VDstIn); in selectWritelane()
1317 .addReg(AMDGPU::SCC); in selectG_ICMP_or_FCMP()
1384 SelectedMI.addReg(Src0Reg); in selectIntrinsicCmp()
1387 SelectedMI.addReg(Src1Reg); in selectIntrinsicCmp()
1420 .addReg(SrcReg); in selectBallot()
1428 .addReg(SrcReg) in selectBallot()
1430 .addReg(HiReg) in selectBallot()
1534 .addReg(LiveIn); in selectReturnAddress()
1600 .addReg(M0Val); in selectDSOrderedIntrinsic()
1606 .addReg(ValReg) in selectDSOrderedIntrinsic()
1698 .addReg(BaseOffset) in selectDSGWSIntrinsic()
1703 .addReg(M0Base); in selectDSGWSIntrinsic()
1713 MIB.addReg(VSrc); in selectDSGWSIntrinsic()
1748 .addReg(PtrBase); in selectDSAppendConsume()
1984 .addReg(TmpReg, RegState::Kill, SubReg); in selectImageIntrinsic()
1993 MIB.addReg(VDataIn); // vdata input in selectImageIntrinsic()
1999 MIB.addReg(SrcOp.getReg()); in selectImageIntrinsic()
2003 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
2005 MIB.addReg(MI.getOperand(ArgOffset + Intr->SampIndex).getReg()); in selectImageIntrinsic()
2137 .addReg(CCReg); in selectG_SELECT()
2237 .addReg(SrcReg, 0, AMDGPU::sub0); in selectG_TRUNC()
2239 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_TRUNC()
2247 .addReg(HiReg) // $src0 in selectG_TRUNC()
2252 .addReg(LoReg, RegState::Implicit); in selectG_TRUNC()
2261 .addReg(HiReg); in selectG_TRUNC()
2264 .addReg(HiReg) in selectG_TRUNC()
2276 .addReg(LoReg) in selectG_TRUNC()
2277 .addReg(ImmReg); in selectG_TRUNC()
2279 .addReg(TmpReg0) in selectG_TRUNC()
2280 .addReg(TmpReg1); in selectG_TRUNC()
2373 .addReg(SrcReg) in selectG_SZA_EXT()
2375 .addReg(UndefReg) in selectG_SZA_EXT()
2392 .addReg(SrcReg); in selectG_SZA_EXT()
2400 .addReg(SrcReg) in selectG_SZA_EXT()
2417 .addReg(SrcReg); in selectG_SZA_EXT()
2429 .addReg(SrcReg, 0, SubReg) in selectG_SZA_EXT()
2437 .addReg(SrcReg, 0, SubReg) in selectG_SZA_EXT()
2439 .addReg(HiReg) in selectG_SZA_EXT()
2458 .addReg(SrcReg, 0, SubReg) in selectG_SZA_EXT()
2460 .addReg(UndefReg) in selectG_SZA_EXT()
2464 .addReg(ExtReg) in selectG_SZA_EXT()
2474 .addReg(SrcReg) in selectG_SZA_EXT()
2479 .addReg(SrcReg) in selectG_SZA_EXT()
2593 .addReg(LoReg) in selectG_CONSTANT()
2595 .addReg(HiReg) in selectG_CONSTANT()
2644 .addReg(Src, 0, AMDGPU::sub0); in selectG_FNEG()
2646 .addReg(Src, 0, AMDGPU::sub1); in selectG_FNEG()
2653 .addReg(HiReg) in selectG_FNEG()
2654 .addReg(ConstReg) in selectG_FNEG()
2657 .addReg(LoReg) in selectG_FNEG()
2659 .addReg(OpReg) in selectG_FNEG()
2686 .addReg(Src, 0, AMDGPU::sub0); in selectG_FABS()
2688 .addReg(Src, 0, AMDGPU::sub1); in selectG_FABS()
2695 .addReg(HiReg) in selectG_FABS()
2696 .addReg(ConstReg) in selectG_FABS()
2699 .addReg(LoReg) in selectG_FABS()
2701 .addReg(OpReg) in selectG_FABS()
2860 .addReg(CondReg) in selectG_BRCOND()
2861 .addReg(Exec) in selectG_BRCOND()
2875 .addReg(CondReg); in selectG_BRCOND()
2924 .addReg(SrcReg) in selectG_PTRMASK()
2925 .addReg(MaskReg) in selectG_PTRMASK()
2950 .addReg(SrcReg) in selectG_PTRMASK()
2951 .addReg(MaskReg); in selectG_PTRMASK()
2964 .addReg(SrcReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2966 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
2979 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2981 .addReg(LoReg) in selectG_PTRMASK()
2982 .addReg(MaskLo); in selectG_PTRMASK()
2993 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
2995 .addReg(HiReg) in selectG_PTRMASK()
2996 .addReg(MaskHi); in selectG_PTRMASK()
3000 .addReg(MaskedLo) in selectG_PTRMASK()
3002 .addReg(MaskedHi) in selectG_PTRMASK()
3077 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
3081 .addReg(SrcReg, 0, SubReg) in selectG_EXTRACT_VECTOR_ELT()
3082 .addReg(SrcReg, RegState::Implicit); in selectG_EXTRACT_VECTOR_ELT()
3092 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
3094 .addReg(SrcReg, 0, SubReg) in selectG_EXTRACT_VECTOR_ELT()
3095 .addReg(SrcReg, RegState::Implicit); in selectG_EXTRACT_VECTOR_ELT()
3103 .addReg(SrcReg) in selectG_EXTRACT_VECTOR_ELT()
3104 .addReg(IdxReg) in selectG_EXTRACT_VECTOR_ELT()
3161 .addReg(IdxReg); in selectG_INSERT_VECTOR_ELT()
3166 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
3167 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
3176 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
3177 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
3178 .addReg(IdxReg) in selectG_INSERT_VECTOR_ELT()
3237 .addReg(VIndex) in selectBufferLoadLds()
3239 .addReg(VOffset) in selectBufferLoadLds()
3242 MIB.addReg(IdxReg); in selectBufferLoadLds()
3244 MIB.addReg(VIndex); in selectBufferLoadLds()
3246 MIB.addReg(VOffset); in selectBufferLoadLds()
3352 .addReg(Addr); in selectGlobalLoadLds()
3355 MIB.addReg(VOffset); in selectGlobalLoadLds()
3457 .addReg(SrcReg); in selectWaveAddress()
3460 .addReg(SrcReg) in selectWaveAddress()
3489 .addReg(SrcReg) in selectStackRestore()
3495 .addReg(WaveAddr); in selectStackRestore()
3703 .addReg(Src); in copyToVGPRIfSrcFolded()
3728 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods0()
3746 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods0()
3771 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods()
3786 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3ModsNonCanonicalizing()
3801 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods()
3814 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3854 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3869 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PModsDOT()
3925 MIB.addReg(Elts[i]); in buildRegSequence()
3988 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF32NegAbs()
4014 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16Neg()
4047 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16NegAbs()
4092 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex8()
4114 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex16()
4127 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3OpSelMods()
4143 MIB.addReg( in selectVINTERPMods()
4161 MIB.addReg( in selectVINTERPModsHi()
4256 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdImm()
4276 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
4287 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgpr()
4288 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectSmrdSgpr()
4298 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgprImm()
4299 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSmrdSgprImm()
4334 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectFlatOffset()
4344 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectGlobalOffset()
4354 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectScratchOffset()
4400 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr in selectGlobalSAddr()
4402 MIB.addReg(HighBits); in selectGlobalSAddr()
4437 MIB.addReg(SAddr); in selectGlobalSAddr()
4440 MIB.addReg(VOffset); in selectGlobalSAddr()
4465 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()
4466 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
4516 .addReg(RHSDef->Reg) in selectScratchSAddr()
4525 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr in selectScratchSAddr()
4591 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4601 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4602 [=](MachineInstrBuilder &MIB) { MIB.addReg(LHS); }, // saddr in selectScratchSVAddr()
4627 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4630 MIB.addReg(HighBits); in selectMUBUFScratchOffen()
4669 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4675 MIB.addReg(VAddr); in selectMUBUFScratchOffen()
4835 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4838 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4860 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4863 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4875 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4920 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDS1Addr1Offset()
4942 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDSReadWrite2()
5025 .addReg(RSrc2) in buildRSRC()
5027 .addReg(RSrc3) in buildRSRC()
5040 .addReg(RSrcLo) in buildRSRC()
5042 .addReg(RSrcHi) in buildRSRC()
5214 MIB.addReg(RSrcReg); in selectMUBUFAddr64()
5217 MIB.addReg(VAddr); in selectMUBUFAddr64()
5221 MIB.addReg(SOffset); in selectMUBUFAddr64()
5223 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFAddr64()
5247 MIB.addReg(RSrcReg); in selectMUBUFOffset()
5251 MIB.addReg(SOffset); in selectMUBUFOffset()
5253 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFOffset()
5272 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectBUFSOffset()
5332 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSMRDBufferSgprImm()
5465 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixModsExt()
5478 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixMods()
5493 .addReg(I.getOperand(2).getReg()); in selectSBarrierSignalIsfirst()
5502 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); in selectSBarrierSignalIsfirst()
5559 .addReg(MemberCount); in selectNamedBarrierInst()
5571 .addReg(BarOp.getReg()) in selectNamedBarrierInst()
5572 .addReg(TmpReg0); in selectNamedBarrierInst()
5582 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::M0).addReg(M0Val); in selectNamedBarrierInst()
5606 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); in selectSBarrierLeave()