647              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
650               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
656              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
658              .addReg(P.first);  in splitMemRef()
660               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
662               .addReg(P.second);  in splitMemRef()
674       .addReg(AdrOp.getReg(), RSA)  in splitMemRef()
740       .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());  in splitCombine()
748       .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());  in splitCombine()
766     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
768     .addReg(Op1.getReg(), RS, Op1.getSubReg())  in splitExt()
806       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
808       .addReg(Op1.getReg(), RS, HiSR);  in splitShift()
831         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
834         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
837         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
843         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
848         .addReg(TmpR)  in splitShift()
849         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
854         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
858         .addReg(TmpR)  in splitShift()
859         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
865       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
871         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
877         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
880         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
883         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
888         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
941       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
942       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);  in splitAslOr()
944       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
945       .addReg(Op2.getReg(), RS2, HiSR);  in splitAslOr()
948       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
949       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
953       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
958       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
959       .addReg(TmpR1);  in splitAslOr()
961       .addReg(TmpR2)  in splitAslOr()
962       .addReg(Op2.getReg(), RS2, HiSR)  in splitAslOr()
970       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
972       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
973       .addReg(Op2.getReg(), RS2, LoSR);  in splitAslOr()
981       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
983       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
984       .addReg(Op2.getReg(), RS2, LoSR)  in splitAslOr()
1113       .addReg(Pr.first)  in collapseRegPairs()
1115       .addReg(Pr.second)  in collapseRegPairs()