Lines Matching refs:addReg
590 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
594 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
596 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
598 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
600 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
659 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
720 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
722 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
724 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
726 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
735 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
779 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
781 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
783 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
785 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
806 MIB.addReg(D0, SrcFlags); in ExpandLaneOp()
808 MIB.addReg(D1, SrcFlags); in ExpandLaneOp()
810 MIB.addReg(D2, SrcFlags); in ExpandLaneOp()
812 MIB.addReg(D3, SrcFlags); in ExpandLaneOp()
827 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
856 MIB.addReg(D0); in ExpandVTBL()
867 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); in ExpandVTBL()
890 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags); in ExpandMQQPRLoadStore()
891 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags); in ExpandMQQPRLoadStore()
892 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags); in ExpandMQQPRLoadStore()
893 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags); in ExpandMQQPRLoadStore()
896 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags); in ExpandMQQPRLoadStore()
897 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags); in ExpandMQQPRLoadStore()
898 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags); in ExpandMQQPRLoadStore()
899 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags); in ExpandMQQPRLoadStore()
903 MIB.addReg(SrcReg, RegState::Implicit); in ExpandMQQPRLoadStore()
1024 .addReg(DstReg) in ExpandTMOV32BitImm()
1039 MIB.addReg(DstReg); in ExpandTMOV32BitImm()
1085 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1086 .addReg(DstReg); in ExpandMOV32BitImm()
1092 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1093 .addReg(DstReg); in ExpandMOV32BitImm()
1106 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1107 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1131 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
1140 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1141 .addReg(DstReg); in ExpandMOV32BitImm()
1145 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
1187 CLRM.addReg(R, RegState::Define); in CMSEClearGPRegs()
1188 CLRM.addReg(ARM::APSR, RegState::Define); in CMSEClearGPRegs()
1189 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1197 .addReg(ClobberReg) in CMSEClearGPRegs()
1203 .addReg(ClobberReg) in CMSEClearGPRegs()
1306 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1313 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1322 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1323 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1330 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1337 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1348 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1353 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1358 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1384 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1385 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1395 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1396 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1422 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1443 .addReg(SaveReg1, RegState::Define) in CMSESaveClearFPRegsV8()
1444 .addReg(SaveReg2, RegState::Define) in CMSESaveClearFPRegsV8()
1445 .addReg(Reg) in CMSESaveClearFPRegsV8()
1457 .addReg(Reg) in CMSESaveClearFPRegsV8()
1475 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1493 .addReg(SaveReg1) in CMSESaveClearFPRegsV8()
1494 .addReg(SaveReg2) in CMSESaveClearFPRegsV8()
1498 .addReg(SaveReg1) in CMSESaveClearFPRegsV8()
1506 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1514 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1518 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1524 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1533 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1537 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1542 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1547 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1568 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1575 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1590 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1593 VPUSH.addReg(Reg); in CMSESaveClearFPRegsV81()
1600 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1642 .addReg(SaveReg1, RegState::Define) in CMSERestoreFPRegsV8()
1643 .addReg(SaveReg2, RegState::Define) in CMSERestoreFPRegsV8()
1644 .addReg(Reg) in CMSERestoreFPRegsV8()
1656 .addReg(Reg) in CMSERestoreFPRegsV8()
1674 .addReg(Reg) in CMSERestoreFPRegsV8()
1675 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1680 .addReg(Reg) in CMSERestoreFPRegsV8()
1681 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1690 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1699 .addReg(ScratchReg, RegState::Define) in CMSERestoreFPRegsV8()
1704 .addReg(ScratchReg) in CMSERestoreFPRegsV8()
1717 .addReg(ARM::S0, RegState::Define) in CMSERestoreFPRegsV8()
1718 .addReg(ARM::S0, RegState::Undef) in CMSERestoreFPRegsV8()
1733 .addReg(SaveReg1) in CMSERestoreFPRegsV8()
1734 .addReg(SaveReg2) in CMSERestoreFPRegsV8()
1738 .addReg(SaveReg1) in CMSERestoreFPRegsV8()
1744 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1769 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
1774 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1781 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1788 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1795 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1798 VPOP.addReg(Reg, RegState::Define); in CMSERestoreFPRegsV81()
1844 .addReg(DesiredReg, RegState::Kill); in ExpandCMP_SWAP()
1857 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1864 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) in ExpandCMP_SWAP()
1865 .addReg(DesiredReg) in ExpandCMP_SWAP()
1871 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1880 .addReg(NewReg) in ExpandCMP_SWAP()
1881 .addReg(AddrReg); in ExpandCMP_SWAP()
1889 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP()
1895 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1930 MIB.addReg(RegLo, Flags); in addExclusiveRegPair()
1931 MIB.addReg(RegHi, Flags); in addExclusiveRegPair()
1933 MIB.addReg(Reg.getReg(), Flags); in addExclusiveRegPair()
1977 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1981 .addReg(DestLo, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
1982 .addReg(DesiredLo) in ExpandCMP_SWAP_64()
1986 .addReg(DestHi, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
1987 .addReg(DesiredHi) in ExpandCMP_SWAP_64()
1988 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1994 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2006 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
2010 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP_64()
2016 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2051 PushMIB.addReg( in CMSEPushCalleeSaves()
2066 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2075 PushMIB2.addReg(Reg, RegState::Kill); in CMSEPushCalleeSaves()
2084 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2088 .addReg(LoReg, RegState::Kill); in CMSEPushCalleeSaves()
2093 .addReg(ARM::SP) in CMSEPushCalleeSaves()
2096 PushMIB.addReg( in CMSEPushCalleeSaves()
2111 PopMIB.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2113 .addReg(ARM::R4 + R, RegState::Kill) in CMSEPopCalleeSaves()
2119 PopMIB2.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2123 .addReg(ARM::SP) in CMSEPopCalleeSaves()
2126 PopMIB.addReg(Reg, RegState::Define); in CMSEPopCalleeSaves()
2177 .addReg(DstReg, in ExpandMI()
2186 .addReg(DstReg, in ExpandMI()
2252 .addReg(JumpTarget.getReg(), RegState::Kill); in ExpandMI()
2283 .addReg(ARM::SP) in ExpandMI()
2304 .addReg(ARM::LR) in ExpandMI()
2343 .addReg(JumpReg) in ExpandMI()
2356 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2357 .addReg(JumpReg) in ExpandMI()
2358 .addReg(ScratchReg) in ExpandMI()
2369 .addReg(JumpReg, RegState::Kill); in ExpandMI()
2539 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
2558 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2600 MIB.addReg(Reg, RegState::Kill); in ExpandMI()
2629 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2630 .addReg(DstReg) in ExpandMI()
2688 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2689 .addReg(DstReg) in ExpandMI()
2723 .addReg(DstReg) in ExpandMI()
2730 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2731 .addReg(DstReg).addImm(LabelId); in ExpandMI()
2766 .addReg(ARM::LR) in ExpandMI()
2770 .addReg(ARM::CPSR, RegState::Undef) in ExpandMI()
2795 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2796 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
2799 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
2827 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) in ExpandMI()
2828 .addReg(D1, SrcIsKill ? RegState::Kill : 0); in ExpandMI()
3185 .addReg(Reg); in ExpandMI()
3192 .addReg(ARM::SP, RegState::Define) in ExpandMI()
3193 .addReg(ARM::SP) in ExpandMI()
3195 .addReg(Reg); in ExpandMI()
3229 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
3231 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()