Lines Matching refs:addReg
164 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
165 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
166 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
170 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
171 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
172 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
198 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
199 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
200 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
207 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
208 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLogic()
209 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandLogic()
259 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogicImm()
260 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expandLogicImm()
273 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogicImm()
274 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expandLogicImm()
315 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
316 .addReg(DstLoReg, getKillRegState(SrcIsKill)); in expand()
320 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
321 .addReg(DstHiReg, getKillRegState(SrcIsKill)); in expand()
374 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
375 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expand()
383 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
384 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expand()
436 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
437 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
444 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
445 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
468 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
469 .addReg(DstHiReg, RegState::Kill); in expand()
475 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
476 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
481 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
482 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
483 .addReg(ZeroReg); in expand()
509 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
510 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
513 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
514 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
541 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
542 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
548 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
549 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expand()
573 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
577 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
624 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
628 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
676 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
686 .addReg(DstLoReg, RegState::Define) in expand()
687 .addReg(SrcReg) in expand()
692 .addReg(DstHiReg, RegState::Define) in expand()
693 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
718 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
719 .addReg(SrcReg, RegState::Define) in expand()
720 .addReg(SrcReg, RegState::Kill); in expand()
724 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
725 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead)) in expand()
726 .addReg(SrcReg, RegState::Kill); in expand()
751 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
752 .addReg(SrcReg, RegState::Define) in expand()
753 .addReg(SrcReg, RegState::Kill); in expand()
757 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
758 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead)) in expand()
759 .addReg(SrcReg, RegState::Kill); in expand()
795 .addReg(SrcReg) in expand()
803 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
811 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg).addReg(SrcReg).addImm(Imm + 2); in expand()
819 .addReg(DstLoReg, RegState::Define) in expand()
820 .addReg(SrcReg) in expand()
826 .addReg(DstHiReg, RegState::Define) in expand()
827 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
853 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank); in expandLPMWELPMW()
864 .addReg(DstLoReg, RegState::Define) in expandLPMWELPMW()
865 .addReg(SrcReg); in expandLPMWELPMW()
868 .addReg(DstHiReg, RegState::Define) in expandLPMWELPMW()
869 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expandLPMWELPMW()
877 .addReg(DstLoReg, RegState::Define) in expandLPMWELPMW()
878 .addReg(AVR::R0, RegState::Kill); in expandLPMWELPMW()
884 .addReg(SrcReg, RegState::Define) in expandLPMWELPMW()
885 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
892 .addReg(SrcLoReg, RegState::Define) in expandLPMWELPMW()
893 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
896 .addReg(SrcHiReg, RegState::Define) in expandLPMWELPMW()
897 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
905 .addReg(DstHiReg, RegState::Define) in expandLPMWELPMW()
906 .addReg(AVR::R0, RegState::Kill); in expandLPMWELPMW()
915 .addReg(SrcReg, RegState::Define) in expandLPMWELPMW()
916 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
923 .addReg(SrcLoReg, RegState::Define) in expandLPMWELPMW()
924 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
927 .addReg(SrcHiReg, RegState::Define) in expandLPMWELPMW()
928 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
960 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(BankReg); in expandLPMBELPMB()
967 .addReg(DstReg, RegState::Define) in expandLPMBELPMB()
968 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expandLPMBELPMB()
976 .addReg(DstReg, RegState::Define) in expandLPMBELPMB()
977 .addReg(AVR::R0, RegState::Kill); in expandLPMBELPMB()
1017 .addReg(STI.getTmpRegister(), RegState::Define) in expandAtomic()
1028 .addReg(STI.getTmpRegister()); in expandAtomic()
1130 MIB0.addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1132 MIB1.addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1136 MIB0.addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1138 MIB1.addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1162 .addReg(DstReg, in expand()
1165 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
1173 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1174 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1177 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1179 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1183 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1185 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1188 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1189 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1214 .addReg(DstReg, RegState::Define) in expand()
1215 .addReg(DstReg, RegState::Kill) in expand()
1216 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1221 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1222 .addReg(DstReg, RegState::Kill) in expand()
1223 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1249 .addReg(DstReg, RegState::Define) in expand()
1250 .addReg(DstReg, RegState::Kill) in expand()
1251 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1256 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1257 .addReg(DstReg, RegState::Kill) in expand()
1258 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1288 .addReg(DstReg, RegState::Kill) in expand()
1294 .addReg(DstReg, getKillRegState(DstIsKill)) in expand()
1295 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
1304 .addReg(DstReg, RegState::Kill) in expand()
1313 .addReg(DstReg) in expand()
1315 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1318 .addReg(DstReg, getKillRegState(DstIsKill)) in expand()
1320 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1324 .addReg(DstReg) in expand()
1326 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1329 .addReg(DstReg, getKillRegState(DstIsKill)) in expand()
1331 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1395 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1400 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1428 .addReg(STI.hasLowByteFirst() ? SrcLoReg : SrcHiReg, in expand()
1432 .addReg(STI.hasLowByteFirst() ? SrcHiReg : SrcLoReg, in expand()
1455 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1460 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1505 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandROLBRd()
1506 .addReg(DstReg, RegState::Kill) in expandROLBRd()
1507 .addReg(DstReg, RegState::Kill); in expandROLBRd()
1511 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandROLBRd()
1512 .addReg(DstReg, getKillRegState(DstIsKill)) in expandROLBRd()
1513 .addReg(ZeroReg); in expandROLBRd()
1548 buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0); in expand()
1551 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg); in expand()
1554 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7); in expand()
1574 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1575 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
1576 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1580 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1581 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
1582 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1607 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1608 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expand()
1609 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1630 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1631 .addReg(DstHiReg, RegState::Kill); in expandLSLW4Rd()
1633 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1634 .addReg(DstLoReg, RegState::Kill); in expandLSLW4Rd()
1639 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1640 .addReg(DstHiReg, RegState::Kill) in expandLSLW4Rd()
1648 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1649 .addReg(DstHiReg, RegState::Kill) in expandLSLW4Rd()
1650 .addReg(DstLoReg); in expandLSLW4Rd()
1657 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1658 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW4Rd()
1666 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1667 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSLW4Rd()
1668 .addReg(DstLoReg); in expandLSLW4Rd()
1687 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW8Rd()
1688 .addReg(DstLoReg); in expandLSLW8Rd()
1693 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW8Rd()
1694 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW8Rd()
1695 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandLSLW8Rd()
1714 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1715 .addReg(DstLoReg); in expandLSLW12Rd()
1719 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1720 .addReg(DstHiReg, RegState::Kill); in expandLSLW12Rd()
1725 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1726 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSLW12Rd()
1734 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1735 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW12Rd()
1736 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandLSLW12Rd()
1775 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1776 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1780 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1781 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1806 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1807 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1828 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1829 .addReg(DstHiReg, RegState::Kill); in expandLSRW4Rd()
1831 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1832 .addReg(DstLoReg, RegState::Kill); in expandLSRW4Rd()
1837 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1838 .addReg(DstLoReg, RegState::Kill) in expandLSRW4Rd()
1846 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1847 .addReg(DstLoReg, RegState::Kill) in expandLSRW4Rd()
1848 .addReg(DstHiReg); in expandLSRW4Rd()
1855 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1856 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSRW4Rd()
1864 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1865 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSRW4Rd()
1866 .addReg(DstHiReg); in expandLSRW4Rd()
1885 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW8Rd()
1886 .addReg(DstHiReg); in expandLSRW8Rd()
1891 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW8Rd()
1892 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSRW8Rd()
1893 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandLSRW8Rd()
1912 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1913 .addReg(DstHiReg); in expandLSRW12Rd()
1917 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1918 .addReg(DstLoReg, RegState::Kill); in expandLSRW12Rd()
1923 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1924 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSRW12Rd()
1932 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1933 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLSRW12Rd()
1934 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandLSRW12Rd()
1985 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1986 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expand()
1990 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1991 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
2016 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2017 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
2042 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2043 .addReg(DstLoReg, RegState::Kill) in expandASRW7Rd()
2044 .addReg(DstLoReg, RegState::Kill); in expandASRW7Rd()
2048 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2049 .addReg(DstHiReg); in expandASRW7Rd()
2053 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2054 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandASRW7Rd()
2055 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandASRW7Rd()
2060 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2061 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandASRW7Rd()
2062 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandASRW7Rd()
2084 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
2085 .addReg(DstHiReg); in expandASRW8Rd()
2089 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
2090 .addReg(DstHiReg, RegState::Kill) in expandASRW8Rd()
2091 .addReg(DstHiReg, RegState::Kill); in expandASRW8Rd()
2096 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
2097 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandASRW8Rd()
2098 .addReg(DstHiReg, getKillRegState(DstIsKill)); in expandASRW8Rd()
2125 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2126 .addReg(DstHiReg, RegState::Kill) in expandASRW14Rd()
2127 .addReg(DstHiReg, RegState::Kill); in expandASRW14Rd()
2131 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2132 .addReg(DstLoReg, RegState::Kill) in expandASRW14Rd()
2133 .addReg(DstLoReg, RegState::Kill); in expandASRW14Rd()
2137 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2138 .addReg(DstHiReg, RegState::Kill) in expandASRW14Rd()
2139 .addReg(DstHiReg, RegState::Kill); in expandASRW14Rd()
2143 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2144 .addReg(DstLoReg); in expandASRW14Rd()
2149 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2150 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandASRW14Rd()
2151 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandASRW14Rd()
2176 .addReg(DstHiReg, RegState::Define) in expandASRW15Rd()
2177 .addReg(DstHiReg, RegState::Kill) in expandASRW15Rd()
2178 .addReg(DstHiReg, RegState::Kill); in expandASRW15Rd()
2183 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW15Rd()
2184 .addReg(DstHiReg, RegState::Kill) in expandASRW15Rd()
2185 .addReg(DstHiReg, RegState::Kill); in expandASRW15Rd()
2193 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW15Rd()
2194 .addReg(DstHiReg); in expandASRW15Rd()
2231 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2232 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2237 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2238 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2239 .addReg(DstReg, RegState::Kill); in expandLSLB7Rd()
2243 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2244 .addReg(DstReg, getKillRegState(DstIsKill)); in expandLSLB7Rd()
2281 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2282 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2283 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2288 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2289 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2290 .addReg(DstReg, RegState::Kill); in expandLSRB7Rd()
2294 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2295 .addReg(DstReg, getKillRegState(DstIsKill)) in expandLSRB7Rd()
2296 .addReg(DstReg, getKillRegState(DstIsKill)); in expandLSRB7Rd()
2333 .addReg(DstReg) in expandASRB6Rd()
2339 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2340 .addReg(DstReg, RegState::Kill) in expandASRB6Rd()
2341 .addReg(DstReg, RegState::Kill); in expandASRB6Rd()
2344 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2345 .addReg(DstReg, RegState::Kill) in expandASRB6Rd()
2346 .addReg(DstReg, RegState::Kill); in expandASRB6Rd()
2349 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2350 .addReg(DstReg, getKillRegState(DstIsKill)) in expandASRB6Rd()
2370 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2371 .addReg(DstReg, RegState::Kill) in expandASRB7Rd()
2372 .addReg(DstReg, RegState::Kill); in expandASRB7Rd()
2376 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2377 .addReg(DstReg, getKillRegState(DstIsKill)) in expandASRB7Rd()
2378 .addReg(DstReg, getKillRegState(DstIsKill)); in expandASRB7Rd()
2430 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2431 .addReg(SrcReg); in expand()
2435 .addReg(DstHiReg, RegState::Define) in expand()
2436 .addReg(SrcReg); in expand()
2442 .addReg(DstHiReg, RegState::Define) in expand()
2443 .addReg(DstHiReg, RegState::Kill) in expand()
2444 .addReg(DstHiReg, RegState::Kill); in expand()
2448 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2449 .addReg(DstHiReg, RegState::Kill) in expand()
2450 .addReg(DstHiReg, RegState::Kill); in expand()
2482 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2483 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expand()
2488 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2489 .addReg(DstHiReg, RegState::Kill | RegState::Undef) in expand()
2490 .addReg(DstHiReg, RegState::Kill | RegState::Undef); in expand()
2512 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2518 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2537 .addReg(STI.getTmpRegister(), RegState::Define) in expand()
2545 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
2550 .addReg(STI.getTmpRegister(), RegState::Kill) in expand()
2555 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()