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Searched refs:SRL (Results 1 – 25 of 119) sorted by relevance

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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha512-mips.pl103 $SRL="dsrl"; # shift right logical
118 $SRL="srl"; # shift right logical
216 $SRL $h,$e,@Sigma1[0]
220 $SRL $tmp0,$e,@Sigma1[1]
224 $SRL $tmp0,$e,@Sigma1[2]
231 $SRL $h,$a,@Sigma0[0]
236 $SRL $tmp0,$a,@Sigma0[1]
240 $SRL $tmp0,$a,@Sigma0[2]
267 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
273 $SRL $tmp3,@X[14],@sigma1[0]
[all …]
H A Dsha512-sparcv9.pl70 $SRL="srlx"; # shift right logical
96 $SRL="srl"; # shift right logical
234 $SRL $e,@Sigma1[0],$h !! $i
238 $SRL $e,@Sigma1[1],$tmp0
242 $SRL $e,@Sigma1[2],$tmp0
249 $SRL $a,@Sigma0[0],$h
254 $SRL $a,@Sigma0[1],$tmp0
258 $SRL $a,@Sigma0[2],$tmp0
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h35 SRL = 0x27,
93 case SRL: in lanaiAluCodeToString()
112 .Case("srl", SRL) in stringToLanaiAluCode()
36 SRL = 0x27, global() enumerator
H A DLanaiISelDAGToDAG.cpp228 case ISD::SRL: in isdToLanaiAluCode()
229 return AluCode::SRL; in isdToLanaiAluCode()
H A DLanaiMemAluCombiner.cpp215 return LPAC::SRL; in mergedAluCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp375 { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
378 { ISD::SRL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
381 { ISD::SRL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
393 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
396 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
399 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
403 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
406 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
418 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand. in getArithmeticInstrCost()
422 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split. in getArithmeticInstrCost()
[all …]
H A DX86ISelDAGToDAG.cpp805 case ISD::SRL: in IsProfitableToFold()
1205 case ISD::SRL: { in PreprocessISelDAG()
1216 case ISD::SRL: NewOpc = X86ISD::VSRLV; break; in PreprocessISelDAG()
2103 if (Shift.getOpcode() != ISD::SRL || in foldMaskAndShiftToExtract()
2118 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); in foldMaskAndShiftToExtract()
2242 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || in foldMaskAndShiftToScale()
2304 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); in foldMaskAndShiftToScale()
2335 if (Shift.getOpcode() != ISD::SRL || in foldMaskedShiftToBEXTR()
2364 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); in foldMaskedShiftToBEXTR()
2597 case ISD::SRL: { in matchAddressRecursively()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelDAGToDAG.cpp162 case ISD::SRL: { in Select()
181 SDNode *SRL = in Select() local
182 CurDAG->getMachineNode(Xtensa::SRL, DL, VT, N0, SDValue(SSR, 0)); in Select()
183 ReplaceNode(Node, SRL); in Select()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp848 case ISD::SRL: { in SimplifyMultipleUseDemandedBits()
1014 assert((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && in combineShiftToAVG()
1093 case ISD::SRL: { in combineShiftToAVG()
1663 if ((Op0Opcode == ISD::SRL || Op0Opcode == ISD::SHL) && Op0.hasOneUse()) { in SimplifyDemandedBits()
1794 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1803 Opc = ISD::SRL; in SimplifyDemandedBits()
1834 if (InnerOp.getOpcode() == ISD::SRL && Op0.hasOneUse() && in SimplifyDemandedBits()
1965 case ISD::SRL: { in SimplifyDemandedBits()
1985 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
2027 isTypeDesirableForOp(ISD::SRL, HalfVT) && in SimplifyDemandedBits()
[all …]
H A DLegalizeIntegerTypes.cpp117 case ISD::SRL: in PromoteIntegerResult()
551 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
629 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
657 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
1139 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
1198 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
1300 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
1605 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt); in PromoteIntRes_FunnelShift()
1607 Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift); in PromoteIntRes_FunnelShift()
1865 DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
[all …]
H A DDAGCombiner.cpp1650 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1945 case ISD::SRL: return visitSRL(N); in visit()
2105 case ISD::SRL: in combine()
2537 BinOpcode == ISD::SRL) && Sel.hasOneUse()) { in foldBinOpIntoSelect()
2759 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2780 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit()
4109 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
4112 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
4374 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
5148 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp86 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
89 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
92 setOperationAction(ISD::SRL, MVT::i32, Custom); in AVRTargetLowering()
243 case ISD::SRL: { in LowerShifts()
257 case ISD::SRL: in LowerShifts()
277 case ISD::SRL: in LowerShifts()
315 case ISD::SRL: in LowerShifts()
333 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
345 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { in LowerShifts()
413 case ISD::SRL: in LowerShifts()
[all …]
/freebsd/crypto/openssl/crypto/bn/asm/
H A Dmips.pl69 $SRL="dsrl";
84 $SRL="srl";
930 $SRL $at,$a1,$t1
945 $SRL $DH,$a2,4*$BNSZ # bits
954 $SRL $HH,$a0,4*$BNSZ # bits
955 $SRL $QT,4*$BNSZ # q=0xffffffff
962 $SRL $at,$a1,4*$BNSZ # bits
987 $SRL $HH,$a0,4*$BNSZ # bits
988 $SRL $QT,4*$BNSZ # q=0xffffffff
995 $SRL $at,$a1,4*$BNSZ # bits
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h133 R_TYPE_INST(SRL);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
/freebsd/sys/contrib/dev/broadcom/brcm80211/brcmsmac/
H A Dmain.h341 u16 SRL; /* 802.11 dot11ShortRetryLimit */ member
542 u16 SRL; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp825 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
1008 SrlX = DAG.getNode(ISD::SRL, DL, SecondOperand->getValueType(0), in performORCombine()
1311 N->getOperand(0).getOpcode() == ISD::SRL) || in shouldFoldConstantShiftPairToMask()
1312 (N->getOpcode() == ISD::SRL && in shouldFoldConstantShiftPairToMask()
2520 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
2521 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in lowerFCOPYSIGN32()
2570 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
2571 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2617 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
2651 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def103 ADD_BINARY_VVP_OP(VVP_SRL,VP_SRL,SRL) REGISTER_PACKED(VVP_SRL)
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZalasr.td69 // to deal with the fact that SRL has addr, data
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp76 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
79 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
222 case ISD::SRL: in LowerOperation()
863 case ISD::SRL: in LowerShifts()
875 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp240 case LPAC::SRL: in getRrMemoryOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp525 ISD::SRA, ISD::SRL, ISD::ROTL, in AMDGPUTargetLowering()
627 ISD::SRA, ISD::SRL, in AMDGPUTargetLowering()
1044 case ISD::SRL: in isNarrowingProfitable()
1086 N->getOpcode() == ISD::SRL) && in isDesirableToCommuteWithShift()
1106 N->user_begin()->getOpcode() == ISD::SRL)) in isDesirableToCommuteWithShift()
2266 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
3608 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerF64ToF16Safe()
3612 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerF64ToF16Safe()
3621 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerF64ToF16Safe()
3653 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerF64ToF16Safe()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h758 SRL, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp661 case ISD::SRL: in getShiftTypeForNode()
743 if (LHSOpcode != ISD::SHL && LHSOpcode != ISD::SRL && LHSOpcode != ISD::SRA) in SelectShiftedRegisterFromAnd()
786 if (LHSOpcode == ISD::SRL && (BitWidth > (NewShiftC + MaskLen))) in SelectShiftedRegisterFromAnd()
789 if (LHSOpcode == ISD::SRL) in SelectShiftedRegisterFromAnd()
2581 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) { in isBitfieldExtractOpFromAnd()
2588 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, in isBitfieldExtractOpFromAnd()
2595 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) { in isBitfieldExtractOpFromAnd()
2651 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
2683 if (N->getOpcode() != ISD::SRL) in isSeveralBitsExtractOpFromShr()
2709 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && in isBitfieldExtractOpFromShr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp366 TwoOperandOpcode == SystemZ::SRL || in processBlock()

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