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Searched refs:SRL (Results 1 – 25 of 110) sorted by relevance

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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha512-mips.pl103 $SRL="dsrl"; # shift right logical
118 $SRL="srl"; # shift right logical
216 $SRL $h,$e,@Sigma1[0]
220 $SRL $tmp0,$e,@Sigma1[1]
224 $SRL $tmp0,$e,@Sigma1[2]
231 $SRL $h,$a,@Sigma0[0]
236 $SRL $tmp0,$a,@Sigma0[1]
240 $SRL $tmp0,$a,@Sigma0[2]
267 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
273 $SRL $tmp3,@X[14],@sigma1[0]
[all …]
H A Dsha512-sparcv9.pl70 $SRL="srlx"; # shift right logical
96 $SRL="srl"; # shift right logical
234 $SRL $e,@Sigma1[0],$h !! $i
238 $SRL $e,@Sigma1[1],$tmp0
242 $SRL $e,@Sigma1[2],$tmp0
249 $SRL $a,@Sigma0[0],$h
254 $SRL $a,@Sigma0[1],$tmp0
258 $SRL $a,@Sigma0[2],$tmp0
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h35 SRL = 0x27,
93 case SRL: in lanaiAluCodeToString()
112 .Case("srl", SRL) in stringToLanaiAluCode()
36 SRL = 0x27, global() enumerator
H A DLanaiISelDAGToDAG.cpp237 case ISD::SRL: in isdToLanaiAluCode()
238 return AluCode::SRL; in isdToLanaiAluCode()
H A DLanaiMemAluCombiner.cpp221 return LPAC::SRL; in mergedAluCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp376 { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
379 { ISD::SRL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
382 { ISD::SRL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
394 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
397 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
400 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
404 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
407 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
419 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand. in getArithmeticInstrCost()
423 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split. in getArithmeticInstrCost()
[all …]
H A DX86ISelDAGToDAG.cpp761 case ISD::SRL: in IsProfitableToFold()
1161 case ISD::SRL: { in PreprocessISelDAG()
1172 case ISD::SRL: NewOpc = X86ISD::VSRLV; break; in PreprocessISelDAG()
2045 if (Shift.getOpcode() != ISD::SRL || in foldMaskAndShiftToExtract()
2060 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); in foldMaskAndShiftToExtract()
2184 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || in foldMaskAndShiftToScale()
2246 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); in foldMaskAndShiftToScale()
2277 if (Shift.getOpcode() != ISD::SRL || in foldMaskedShiftToBEXTR()
2306 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); in foldMaskedShiftToBEXTR()
2540 case ISD::SRL: { in matchAddressRecursively()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp959 assert((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && in combineShiftToAVG()
1038 case ISD::SRL: { in combineShiftToAVG()
1615 if ((Op0Opcode == ISD::SRL || Op0Opcode == ISD::SHL) && Op0.hasOneUse()) { in SimplifyDemandedBits()
1747 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1756 Opc = ISD::SRL; in SimplifyDemandedBits()
1787 if (InnerOp.getOpcode() == ISD::SRL && Op0.hasOneUse() && in SimplifyDemandedBits()
1928 case ISD::SRL: { in SimplifyDemandedBits()
1948 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1974 isTypeDesirableForOp(ISD::SRL, HalfVT) && in SimplifyDemandedBits()
1976 (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) && in SimplifyDemandedBits()
[all …]
H A DLegalizeIntegerTypes.cpp114 case ISD::SRL: in PromoteIntegerResult()
534 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
589 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
617 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
1090 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
1153 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
1255 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
1560 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt); in PromoteIntRes_FunnelShift()
1562 Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift); in PromoteIntRes_FunnelShift()
1820 DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
[all …]
H A DDAGCombiner.cpp1593 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1887 case ISD::SRL: return visitSRL(N); in visit()
2036 case ISD::SRL: in combine()
2452 BinOpcode == ISD::SRL) && Sel.hasOneUse()) { in foldBinOpIntoSelect()
2597 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2618 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit()
3840 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3843 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
4070 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
4814 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike()
[all …]
H A DLegalizeVectorOps.cpp364 case ISD::SRL: in LegalizeOp()
1345 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBSWAP()
1383 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && in ExpandBITREVERSE()
1400 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBITREVERSE()
1601 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) { in ExpandUINT_TO_FLOAT()
1628 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord); in ExpandUINT_TO_FLOAT()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp87 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
90 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
93 setOperationAction(ISD::SRL, MVT::i32, Custom); in AVRTargetLowering()
296 case ISD::SRL: { in LowerShifts()
310 case ISD::SRL: in LowerShifts()
330 case ISD::SRL: in LowerShifts()
368 case ISD::SRL: in LowerShifts()
386 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
398 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { in LowerShifts()
470 case ISD::SRL: in LowerShifts()
[all …]
/freebsd/crypto/openssl/crypto/bn/asm/
H A Dmips.pl69 $SRL="dsrl";
84 $SRL="srl";
930 $SRL $at,$a1,$t1
945 $SRL $DH,$a2,4*$BNSZ # bits
954 $SRL $HH,$a0,4*$BNSZ # bits
955 $SRL $QT,4*$BNSZ # q=0xffffffff
962 $SRL $at,$a1,4*$BNSZ # bits
987 $SRL $HH,$a0,4*$BNSZ # bits
988 $SRL $QT,4*$BNSZ # q=0xffffffff
995 $SRL $at,$a1,4*$BNSZ # bits
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h133 R_TYPE_INST(SRL);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp816 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
956 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
1220 N->getOperand(0).getOpcode() == ISD::SRL) || in shouldFoldConstantShiftPairToMask()
1221 (N->getOpcode() == ISD::SRL && in shouldFoldConstantShiftPairToMask()
2379 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
2380 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in lowerFCOPYSIGN32()
2429 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
2430 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2476 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
2510 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def103 ADD_BINARY_VVP_OP(VVP_SRL,VP_SRL,SRL) REGISTER_PACKED(VVP_SRL)
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp128 setOperationAction(ISD::SRL, MVT::i32, Custom); in LoongArchTargetLowering()
264 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
311 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
338 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
2547 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in lowerShiftLeftParts()
2549 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt); in lowerShiftLeftParts()
2588 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
2597 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
2630 case ISD::SRL: in getLoongArchWOpcode()
2828 case ISD::SRL: in ReplaceNodeResults()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp242 case LPAC::SRL: in getRrMemoryOpValue()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h735 SRL, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp77 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
80 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
343 case ISD::SRL: in LowerOperation()
985 case ISD::SRL: in LowerShifts()
997 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp512 ISD::SRA, ISD::SRL, ISD::ROTL, in AMDGPUTargetLowering()
614 ISD::SRA, ISD::SRL, in AMDGPUTargetLowering()
1032 N->getOpcode() == ISD::SRL) && in isDesirableToCommuteWithShift()
1043 N->use_begin()->getOpcode() == ISD::SRL)) in isDesirableToCommuteWithShift()
2209 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
3543 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
3547 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3556 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3588 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
3596 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp661 case ISD::SRL: in getShiftTypeForNode()
739 if (LHSOpcode != ISD::SHL && LHSOpcode != ISD::SRL && LHSOpcode != ISD::SRA) in SelectShiftedRegisterFromAnd()
782 if (LHSOpcode == ISD::SRL && (BitWidth > (NewShiftC + MaskLen))) in SelectShiftedRegisterFromAnd()
785 if (LHSOpcode == ISD::SRL) in SelectShiftedRegisterFromAnd()
2481 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) { in isBitfieldExtractOpFromAnd()
2488 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, in isBitfieldExtractOpFromAnd()
2495 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) { in isBitfieldExtractOpFromAnd()
2551 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
2583 if (N->getOpcode() != ISD::SRL) in isSeveralBitsExtractOpFromShr()
2609 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && in isBitfieldExtractOpFromShr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp369 TwoOperandOpcode == SystemZ::SRL || in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1705 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { in LowerAndToBTST()
1840 if (Op.getOperand(0).getOpcode() != ISD::SRL) in LowerTruncateToBTST()
1951 case ISD::SRL: in EmitTest()
1963 APInt Mask = ArithOp.getOpcode() == ISD::SRL in EmitTest()
3455 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in LowerShiftLeftParts()
3457 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt); in LowerShiftLeftParts()
3495 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in LowerShiftRightParts()
3506 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in LowerShiftRightParts()

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