Lines Matching refs:SRL
512 ISD::SRA, ISD::SRL, ISD::ROTL, in AMDGPUTargetLowering()
614 ISD::SRA, ISD::SRL, in AMDGPUTargetLowering()
1032 N->getOpcode() == ISD::SRL) && in isDesirableToCommuteWithShift()
1043 N->use_begin()->getOpcode() == ISD::SRL)) in isDesirableToCommuteWithShift()
2209 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
3543 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
3547 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3556 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3588 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
3596 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
3611 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
4113 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
4114 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
4133 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
4167 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) { in performTruncateCombine()
4193 (Src.getOpcode() == ISD::SRL || in performTruncateCombine()
5119 case ISD::SRL: { in PerformDAGCombine()
5220 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()
5377 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()