Lines Matching refs:SRL
1593 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1887 case ISD::SRL: return visitSRL(N); in visit()
2036 case ISD::SRL: in combine()
2452 BinOpcode == ISD::SRL) && Sel.hasOneUse()) { in foldBinOpIntoSelect()
2597 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2618 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit()
3840 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3843 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
4070 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
4814 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike()
4920 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitUDIVLike()
4936 return DAG.getNode(ISD::SRL, DL, VT, N0, Add); in visitUDIVLike()
5008 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && in visitREM()
5106 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
5154 hasOperation(ISD::SRL, VT)) { in visitMULHU()
5161 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitMULHU()
5176 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
5228 return DAG.getNode(ISD::SRL, DL, VT, X, in visitAVG()
5387 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
5440 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
5832 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL || in hoistLogicOpWithSameOpcodeHands()
6383 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
6728 InnerShift = ISD::SRL; in unfoldExtremeBitClearingToShifts()
6729 else if (OuterShift == ISD::SRL) in unfoldExtremeBitClearingToShifts()
6788 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6872 !(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL || in foldLogicOfShifts()
7370 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
7397 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
7399 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
7465 Res = DAG.getNode(ISD::SRL, DL, VT, Res, in MatchBSwapHWordLow()
7482 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
7487 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
7508 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { in isBSwapHWordElement()
7522 if (Opc0 != ISD::SRL) in isBSwapHWordElement()
7567 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
7603 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
7684 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt)); in MatchBSwapHWord()
7808 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
8031 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
8066 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) in extractShiftForRotate()
8080 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
8105 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
8106 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
8362 if (IsBinOpImm(N1, ISD::SRL, 1) && in MatchFunnelPosNeg()
8477 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) in MatchRotate()
8498 SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt); in MatchRotate()
8547 SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt); in MatchRotate()
8950 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
9734 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
9989 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
10010 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { in visitSHL()
10042 if (N0.getOpcode() == ISD::SRL && in visitSHL()
10052 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, Diff); in visitSHL()
10053 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); in visitSHL()
10175 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
10204 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) { in combineShiftToMULH()
10409 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, in visitSRA()
10475 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
10501 return DAG.getNode(ISD::SRL, DL, VT, N0, N1); in visitSRA()
10531 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, DL, VT, {N0, N1})) in visitSRL()
10549 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
10569 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum); in visitSRL()
10574 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
10589 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL()
10598 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL()
10627 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N01); in visitSRL()
10638 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N1); in visitSRL()
10639 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); in visitSRL()
10653 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
10657 DAG.getNode(ISD::SRL, DL0, SmallVT, N0.getOperand(0), in visitSRL()
10671 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1); in visitSRL()
10701 Op = DAG.getNode(ISD::SRL, DL, VT, Op, in visitSRL()
10713 return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1); in visitSRL()
10814 ISD::SRL, DL, VT, N1, in visitFunnelShift()
10868 return DAG.getNode(ISD::SRL, DL, VT, N1, N2); in visitFunnelShift()
11072 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitBSWAP()
11078 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; in visitBSWAP()
11110 if ((!LegalOperations || TLI.isOperationLegal(ISD::SRL, VT)) && in visitBITREVERSE()
11112 return DAG.getNode(ISD::SRL, DL, VT, X, Y); in visitBITREVERSE()
11187 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SHL) { in visitCTPOP()
11192 if ((N0.getOpcode() == ISD::SRL && in visitCTPOP()
12682 (B.getOpcode() == ISD::SRL || B.getOpcode() == ISD::SHL) && in visitSETCC()
12752 if (NewShiftOpc == ISD::SHL || NewShiftOpc == ISD::SRL) { in visitSETCC()
13147 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
13433 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
14110 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
14450 } else if (Opc == ISD::SRL || Opc == ISD::SRA) { in reduceLoadWidth()
14468 ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD; in reduceLoadWidth()
14503 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
14504 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; in reduceLoadWidth() local
14510 if (!SRL.hasOneUse()) in reduceLoadWidth()
14515 auto *LN = dyn_cast<LoadSDNode>(SRL.getOperand(0)); in reduceLoadWidth()
14516 auto *SRL1C = dyn_cast<ConstantSDNode>(SRL.getOperand(1)); in reduceLoadWidth()
14550 SDNode *Mask = *(SRL->use_begin()); in reduceLoadWidth()
14551 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && in reduceLoadWidth()
14560 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) in reduceLoadWidth()
14569 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) { in reduceLoadWidth()
14577 N0 = SRL.getOperand(0); in reduceLoadWidth()
14753 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
15538 X = DAG.getNode(ISD::SRL, DL, in visitBITCAST()
15647 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) in visitFREEZE()
18276 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
18279 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
19018 TLI.isOperationLegal(ISD::SRL, STType)) { in ForwardStoreValueToDirectLoad()
19019 Val = DAG.getNode(ISD::SRL, SDLoc(LD), STType, Val, in ForwardStoreValueToDirectLoad()
19663 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
19845 ISD::SRL, DL, IVal.getValueType(), IVal, in ShrinkLoadReplaceStoreWithStore()
22480 case ISD::SRL: in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
23046 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
27472 SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt); in foldSelectCCToShiftAnd()