Lines Matching refs:SRL
376 { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
379 { ISD::SRL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
382 { ISD::SRL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
394 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
397 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
400 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
404 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
407 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
419 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand. in getArithmeticInstrCost()
423 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split. in getArithmeticInstrCost()
427 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, // psrld in getArithmeticInstrCost()
430 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, // psrld in getArithmeticInstrCost()
435 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, // psrlq in getArithmeticInstrCost()
438 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, // psrlq in getArithmeticInstrCost()
455 { ISD::SRL, MVT::v16i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
458 { ISD::SRL, MVT::v32i8, { 2, 8, 2, 4 } }, // psrlw + pand. in getArithmeticInstrCost()
462 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
465 { ISD::SRL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psrlw in getArithmeticInstrCost()
469 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld in getArithmeticInstrCost()
472 { ISD::SRL, MVT::v8i32, { 2, 2, 1, 2 } }, // psrld in getArithmeticInstrCost()
476 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq in getArithmeticInstrCost()
479 { ISD::SRL, MVT::v4i64, { 2, 2, 1, 2 } }, // psrlq in getArithmeticInstrCost()
496 { ISD::SRL, MVT::v16i8, { 2, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
499 { ISD::SRL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psrlw + pand) + split. in getArithmeticInstrCost()
503 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 1 } }, // psrlw. in getArithmeticInstrCost()
506 { ISD::SRL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psrlw + split. in getArithmeticInstrCost()
510 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 1 } }, // psrld. in getArithmeticInstrCost()
513 { ISD::SRL, MVT::v8i32, { 3, 6, 4, 5 } }, // psrld + split. in getArithmeticInstrCost()
517 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 1 } }, // psrlq. in getArithmeticInstrCost()
520 { ISD::SRL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split. in getArithmeticInstrCost()
539 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
543 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw. in getArithmeticInstrCost()
547 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld. in getArithmeticInstrCost()
551 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq. in getArithmeticInstrCost()
688 { ISD::SRL, MVT::v16i8, { 3,10, 5, 8 } }, // psrlw + pand. in getArithmeticInstrCost()
691 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand. in getArithmeticInstrCost()
694 { ISD::SRL, MVT::v64i8, { 4, 8, 7,10 } }, // psrlw + pand. in getArithmeticInstrCost()
698 { ISD::SRL, MVT::v32i16, { 2, 4, 2, 3 } }, // psrlw in getArithmeticInstrCost()
710 { ISD::SRL, MVT::v32i16, { 5,10, 5, 7 } }, // psrlw + split. in getArithmeticInstrCost()
714 { ISD::SRL, MVT::v16i32, { 2, 4, 2, 3 } }, // psrld in getArithmeticInstrCost()
719 { ISD::SRL, MVT::v4i64, { 1, 4, 1, 2 } }, // psrlq in getArithmeticInstrCost()
722 { ISD::SRL, MVT::v8i64, { 1, 4, 1, 2 } }, // psrlq in getArithmeticInstrCost()
735 { ISD::SRL, MVT::v16i8, { 3, 9, 5, 8 } }, // psrlw + pand. in getArithmeticInstrCost()
738 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand. in getArithmeticInstrCost()
742 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 2 } }, // psrlw. in getArithmeticInstrCost()
745 { ISD::SRL, MVT::v16i16, { 2, 4, 2, 3 } }, // psrlw. in getArithmeticInstrCost()
749 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 2 } }, // psrld in getArithmeticInstrCost()
752 { ISD::SRL, MVT::v8i32, { 2, 4, 2, 3 } }, // psrld in getArithmeticInstrCost()
756 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 2 } }, // psrlq in getArithmeticInstrCost()
759 { ISD::SRL, MVT::v4i64, { 2, 4, 1, 2 } }, // psrlq in getArithmeticInstrCost()
771 { ISD::SRL, MVT::v16i8, { 4, 8, 5, 8 } }, // psrlw + pand. in getArithmeticInstrCost()
774 { ISD::SRL, MVT::v32i8, { 7, 9,10,14 } }, // psrlw + pand + split. in getArithmeticInstrCost()
778 { ISD::SRL, MVT::v8i16, { 1, 3, 1, 2 } }, // psrlw. in getArithmeticInstrCost()
781 { ISD::SRL, MVT::v16i16, { 3, 7, 5, 7 } }, // psrlw + split. in getArithmeticInstrCost()
785 { ISD::SRL, MVT::v4i32, { 1, 3, 1, 2 } }, // psrld. in getArithmeticInstrCost()
788 { ISD::SRL, MVT::v8i32, { 3, 7, 5, 7 } }, // psrld + split. in getArithmeticInstrCost()
792 { ISD::SRL, MVT::v2i64, { 1, 3, 1, 2 } }, // psrlq. in getArithmeticInstrCost()
795 { ISD::SRL, MVT::v4i64, { 3, 7, 4, 6 } }, // psrlq + split. in getArithmeticInstrCost()
810 { ISD::SRL, MVT::v16i8, { 9, 13, 5, 9 } }, // psrlw + pand. in getArithmeticInstrCost()
814 { ISD::SRL, MVT::v8i16, { 2, 2, 1, 2 } }, // psrlw. in getArithmeticInstrCost()
818 { ISD::SRL, MVT::v4i32, { 2, 2, 1, 2 } }, // psrld. in getArithmeticInstrCost()
822 { ISD::SRL, MVT::v2i64, { 2, 2, 1, 2 } }, // psrlq. in getArithmeticInstrCost()
847 { ISD::SRL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsrlvw/pack sequence. in getArithmeticInstrCost()
850 { ISD::SRL, MVT::v32i8, { 4, 30,12,18 } }, // extend/vpsrlvw/pack sequence. in getArithmeticInstrCost()
853 { ISD::SRL, MVT::v64i8, { 7, 27,15,18 } }, // extend/vpsrlvw/pack sequence. in getArithmeticInstrCost()
857 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsrlvw in getArithmeticInstrCost()
860 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsrlvw in getArithmeticInstrCost()
863 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsrlvw in getArithmeticInstrCost()
896 { ISD::SRL, MVT::v64i8, { 15, 19,30,36 } }, // vpblendv+split sequence. in getArithmeticInstrCost()
900 { ISD::SRL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
904 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
907 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
910 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
914 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
917 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
920 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
992 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsrlvd (Haswell from agner.org) in getArithmeticInstrCost()
995 { ISD::SRL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsrlvd (Haswell from agner.org) in getArithmeticInstrCost()
998 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsrlvq (Haswell from agner.org) in getArithmeticInstrCost()
1000 { ISD::SRL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsrlvq (Haswell from agner.org) in getArithmeticInstrCost()
1028 { ISD::SRL, MVT::v16i8, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
1031 { ISD::SRL, MVT::v8i16, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
1034 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
1037 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
1041 { ISD::SRL, MVT::v32i8, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1044 { ISD::SRL, MVT::v16i16, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1047 { ISD::SRL, MVT::v8i32, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1050 { ISD::SRL, MVT::v4i64, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1059 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && Op2Info.isConstant()) in getArithmeticInstrCost()
1123 { ISD::SRL, MVT::v16i8, { 6, 27,12,18 } }, // vpblendvb sequence. in getArithmeticInstrCost()
1124 { ISD::SRL, MVT::v32i8, { 8, 30,12,24 } }, // vpblendvb sequence. in getArithmeticInstrCost()
1125 { ISD::SRL, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
1126 { ISD::SRL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
1238 { ISD::SRL, MVT::v16i8, { 11, 27,12,18 } }, // pblendvb sequence. in getArithmeticInstrCost()
1239 { ISD::SRL, MVT::v32i8, { 23, 23,30,43 } }, // pblendvb sequence + split. in getArithmeticInstrCost()
1240 { ISD::SRL, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence. in getArithmeticInstrCost()
1241 { ISD::SRL, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split. in getArithmeticInstrCost()
1242 { ISD::SRL, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1243 { ISD::SRL, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split. in getArithmeticInstrCost()
1244 { ISD::SRL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1245 { ISD::SRL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split. in getArithmeticInstrCost()
1327 { ISD::SRL, MVT::v16i8, { 16, 27,18,24 } }, // pblendvb sequence. in getArithmeticInstrCost()
1328 { ISD::SRL, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence. in getArithmeticInstrCost()
1329 { ISD::SRL, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1330 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence. in getArithmeticInstrCost()
1362 { ISD::SRL, MVT::v16i8, { 14, 28,27,30 } }, // cmpgtb sequence. in getArithmeticInstrCost()
1363 { ISD::SRL, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence. in getArithmeticInstrCost()
1364 { ISD::SRL, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1365 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence. in getArithmeticInstrCost()