Lines Matching refs:SRL

128     setOperationAction(ISD::SRL, MVT::i32, Custom);  in LoongArchTargetLowering()
264 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
311 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
338 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
2547 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in lowerShiftLeftParts()
2549 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt); in lowerShiftLeftParts()
2588 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
2597 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
2630 case ISD::SRL: in getLoongArchWOpcode()
2828 case ISD::SRL: in ReplaceNodeResults()
3125 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
3180 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL || lsb == 0) in performANDCombine()
3308 DAG.getNode(ISD::SRL, DL, N1->getValueType(0), N1, in performORCombine()
3433 DAG.getNode(ISD::SRL, DL, N1->getValueType(0), in performORCombine()
4019 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
4023 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
4027 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
4031 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
4035 return DAG.getNode(ISD::SRL, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
4242 case ISD::SRL: in PerformDAGCombine()