Lines Matching refs:SRL
959 assert((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && in combineShiftToAVG()
1038 case ISD::SRL: { in combineShiftToAVG()
1615 if ((Op0Opcode == ISD::SRL || Op0Opcode == ISD::SHL) && Op0.hasOneUse()) { in SimplifyDemandedBits()
1747 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1756 Opc = ISD::SRL; in SimplifyDemandedBits()
1787 if (InnerOp.getOpcode() == ISD::SRL && Op0.hasOneUse() && in SimplifyDemandedBits()
1928 case ISD::SRL: { in SimplifyDemandedBits()
1948 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1974 isTypeDesirableForOp(ISD::SRL, HalfVT) && in SimplifyDemandedBits()
1976 (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) && in SimplifyDemandedBits()
1983 TLO.DAG.getNode(ISD::SRL, dl, HalfVT, NewOp, NewShiftAmt); in SimplifyDemandedBits()
2003 SDValue NewOp = TLO.DAG.getNode(ISD::SRL, dl, VT, DemandedOp0, Op1); in SimplifyDemandedBits()
2037 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
2099 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); in SimplifyDemandedBits()
2106 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); in SimplifyDemandedBits()
2224 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) && in SimplifyDemandedBits()
2227 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
2320 unsigned ShiftOpcode = NLZ > NTZ ? ISD::SRL : ISD::SHL; in SimplifyDemandedBits()
2580 case ISD::SRL: in SimplifyDemandedBits()
2583 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
2617 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, NewShAmt)); in SimplifyDemandedBits()
3617 case ISD::SRL: in SimplifyDemandedVectorElts()
4185 NewShiftOpcode = ISD::SRL; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4187 case ISD::SRL: in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4448 SDValue Shift = DAG.getNode(ISD::SRL, dl, OpVT, Y, NewShAmt); in foldSetCCWithFunnelShift()
4530 if (N0.getOpcode() == ISD::SRL && (C1.isZero() || C1.isOne()) && in SimplifySetCC()
5123 DAG.getNode(ISD::SRL, dl, ShValTy, N0, in SimplifySetCC()
5134 DAG.getNode(ISD::SRL, dl, ShValTy, N0, in SimplifySetCC()
5152 ISD::SRL, dl, ShValTy, N0.getOperand(0), in SimplifySetCC()
5181 DAG.getNode(ISD::SRL, dl, ShValTy, N0, in SimplifySetCC()
6211 Res = DAG.getNode(ISD::SRL, dl, VT, Res, Shift, Flags); in BuildExactUDIV()
6390 Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, in BuildSDIV()
6412 Y = DAG.getNode(ISD::SRL, dl, WideVT, Y, in BuildSDIV()
6437 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift); in BuildSDIV()
6561 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift); in BuildUDIV()
6573 Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, in BuildUDIV()
6595 Y = DAG.getNode(ISD::SRL, dl, WideVT, Y, in BuildUDIV()
6618 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT)); in BuildUDIV()
6627 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift); in BuildUDIV()
7629 isOperationLegalOrCustom(ISD::SRL, VT) && in expandMUL_LOHI()
7631 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift); in expandMUL_LOHI()
7633 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); in expandMUL_LOHI()
7687 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); in expandMUL_LOHI()
7712 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); in expandMUL_LOHI()
7829 DAG.getNode(ISD::SRL, dl, HiLoVT, LL, in expandDIVREMByConstant()
7834 LH = DAG.getNode(ISD::SRL, dl, HiLoVT, LH, in expandDIVREMByConstant()
7981 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandFunnelShift()
8011 X = DAG.getNode(ISD::SRL, DL, VT, X, One); in expandFunnelShift()
8031 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt); in expandFunnelShift()
8050 SDValue ShY1 = DAG.getNode(ISD::SRL, DL, VT, Y, One); in expandFunnelShift()
8051 ShY = DAG.getNode(ISD::SRL, DL, VT, ShY1, InvShAmt); in expandFunnelShift()
8055 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, ShAmt); in expandFunnelShift()
8084 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandROT()
8090 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT()
8091 unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL; in expandROT()
8149 Tmp3 = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt); in expandShiftParts()
8205 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
8226 DAG.getNode(ISD::SRL, dl, DstVT, R, in expandFP_TO_SINT()
8359 if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) || in expandUINT_TO_FP()
8382 SDValue Hi = DAG.getNode(ISD::SRL, dl, SrcVT, Src, HiShift); in expandUINT_TO_FP()
8825 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in canExpandVectorCTPOP()
8858 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8864 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8870 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8884 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8904 return DAG.getNode(ISD::SRL, dl, VT, V, DAG.getConstant(Len - 8, dl, ShVT)); in expandCTPOP()
9004 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandCTLZ()
9020 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp)); in expandCTLZ()
9066 ISD::SRL, DL, VT, in CTTZTableLookup()
9310 unsigned ShiftOpc = IsSigned ? ISD::SRA : ISD::SRL; in expandAVG()
9342 Avg = DAG.getNode(ISD::SRL, dl, ExtVT, Avg, in expandAVG()
9382 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
9384 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in expandBSWAP()
9399 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
9402 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in expandBSWAP()
9405 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); in expandBSWAP()
9408 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); in expandBSWAP()
9517 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(4, dl, SHVT)); in expandBITREVERSE()
9524 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(2, dl, SHVT)); in expandBITREVERSE()
9531 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(1, dl, SHVT)); in expandBITREVERSE()
9546 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT)); in expandBITREVERSE()
9666 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
10048 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in expandUnalignedStore()
10237 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, in lowerCmpEqZeroToCtlzSrl()
10499 DAG.getNode(IsSigned ? ISD::SRA : ISD::SRL, dl, VT, Result, RHS); in expandShlSat()
10551 SDValue TH = DAG.getNode(ISD::SRL, dl, VT, T, Shift); in forceExpandWideMUL()
10552 SDValue LLH = DAG.getNode(ISD::SRL, dl, VT, LL, Shift); in forceExpandWideMUL()
10553 SDValue RLH = DAG.getNode(ISD::SRL, dl, VT, RL, Shift); in forceExpandWideMUL()
10558 SDValue UH = DAG.getNode(ISD::SRL, dl, VT, U, Shift); in forceExpandWideMUL()
10562 SDValue VH = DAG.getNode(ISD::SRL, dl, VT, V, Shift); in forceExpandWideMUL()
10829 RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS, in expandFixedPointDiv()
10976 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL, in expandMULO()
11008 DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt)); in expandMULO()
11299 SignBit = DAG.getNode(ISD::SRL, dl, WideIntVT, SignBit, ShiftCnst); in expandRoundInexactToOdd()
11337 SDValue Lsb = DAG.getNode(ISD::SRL, dl, I32, Op, in expandFP_ROUND()
11349 Op = DAG.getNode(ISD::SRL, dl, I32, Op, in expandFP_ROUND()