Lines Matching refs:SRL
816 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
956 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
1220 N->getOperand(0).getOpcode() == ISD::SRL) || in shouldFoldConstantShiftPairToMask()
1221 (N->getOpcode() == ISD::SRL && in shouldFoldConstantShiftPairToMask()
2379 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
2380 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in lowerFCOPYSIGN32()
2429 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
2430 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2476 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
2510 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
2618 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, in lowerShiftLeftParts()
2620 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); in lowerShiftLeftParts()
2660 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
2662 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, in lowerShiftRightParts()
2763 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in lowerLOAD() local
2764 SDValue Ops[] = { SRL, LWR.getValue(1) }; in lowerLOAD()
3548 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; in LowerCallResult()
3602 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; in UnpackFromArgumentSlot()