Home
last modified time | relevance | path

Searched refs:ISD (Results 1 – 25 of 238) sorted by relevance

12345678910

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp61 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
80 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
82 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
83 case ISD::MEMBARRIER: return "MemBarrier"; in getOperationName()
84 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
85 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
86 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; in getOperationName()
87 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
88 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
89 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
[all …]
H A DLegalizeVectorOps.cpp287 case ISD::LOAD: { in LegalizeOp()
289 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
291 if (LoadedVT.isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
295 case ISD::STORE: { in LegalizeOp()
303 case ISD::MERGE_VALUES: in LegalizeOp()
311 case ISD::STRICT_##DAGN: in LegalizeOp()
314 if (Op.getOpcode() == ISD::STRICT_SINT_TO_FP || in LegalizeOp()
315 Op.getOpcode() == ISD::STRICT_UINT_TO_FP) in LegalizeOp()
317 if (Op.getOpcode() == ISD::STRICT_FSETCC || in LegalizeOp()
318 Op.getOpcode() == ISD::STRICT_FSETCCS) { in LegalizeOp()
[all …]
H A DLegalizeIntegerTypes.cpp58 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
59 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
60 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
61 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
62 case ISD::VP_BITREVERSE: in PromoteIntegerResult()
63 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
64 case ISD::VP_BSWAP: in PromoteIntegerResult()
65 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
66 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
67 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
[all …]
H A DLegalizeDAG.cpp341 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
357 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
394 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
412 if (!ISD::isNormalStore(ST)) in OptimizeFloatStore()
430 if (Value.getOpcode() == ISD::TargetConstantFP) in OptimizeFloatStore()
470 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); in OptimizeFloatStore()
495 switch (TLI.getOperationAction(ISD::STORE, VT)) { in LegalizeStoreOps()
519 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT); in LegalizeStoreOps()
522 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
577 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
[all …]
H A DTargetLowering.cpp99 if (Value->getOpcode() == ISD::AssertZext) in parametersInCSRMatch()
101 if (Value->getOpcode() != ISD::CopyFromReg) in parametersInCSRMatch()
243 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
247 isOperationLegalOrCustom(ISD::STORE, MVT::f64) && in findOptimalMemOpLowering()
293 ISD::CondCode &CCCode, in softenSetCCOperands()
303 ISD::CondCode &CCCode, in softenSetCCOperands()
319 case ISD::SETEQ: in softenSetCCOperands()
320 case ISD::SETOEQ: in softenSetCCOperands()
325 case ISD::SETNE: in softenSetCCOperands()
326 case ISD::SETUNE: in softenSetCCOperands()
[all …]
H A DLegalizeVectorTypes.cpp56 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
57 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
58 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
59 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
60 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
61 case ISD::AssertZext: in ScalarizeVectorResult()
62 case ISD::AssertSext: in ScalarizeVectorResult()
63 case ISD::FPOWI: in ScalarizeVectorResult()
66 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
67 case ISD in ScalarizeVectorResult()
[all...]
H A DLegalizeFloatTypes.cpp64 case ISD::EXTRACT_ELEMENT: R = SoftenFloatRes_EXTRACT_ELEMENT(N); break; in SoftenFloatResult()
65 case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break; in SoftenFloatResult()
66 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
67 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult()
68 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
69 case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N); break; in SoftenFloatResult()
70 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
72 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
73 case ISD::STRICT_FMINNUM: in SoftenFloatResult()
74 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
[all …]
H A DDAGCombiner.cpp272 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
277 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
406 ISD::CondCode CC);
592 SDValue N2, SDValue N3, ISD::CondCode CC,
596 ISD::CondCode CC);
599 SDValue N2, SDValue N3, ISD::CondCode CC);
608 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
720 case ISD::Constant: in getStoreSource()
721 case ISD::ConstantFP: in getStoreSource()
723 case ISD::BUILD_VECTOR: in getStoreSource()
[all …]
H A DSelectionDAG.cpp145 bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { in isConstantSplatVector()
146 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
180 bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllOnes()
182 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllOnes()
185 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllOnes()
190 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllOnes()
229 bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllZeros()
231 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllZeros()
234 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllZeros()
239 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllZeros()
[all …]
H A DMatchContext.h63 if (auto RootMaskPos = ISD::getVPMaskIdx(Root->getOpcode())) in VPMatchContext()
65 else if (Root->getOpcode() == ISD::VP_SELECT) in VPMatchContext()
69 if (auto RootVLenPos = ISD::getVPExplicitVectorLengthIdx(Root->getOpcode())) in VPMatchContext()
74 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( in getRootBaseOpcode()
86 auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), in match()
93 if (auto MaskPos = ISD::getVPMaskIdx(VPOpcode)) { in match()
96 !ISD::isConstantSplatVectorAllOnes(MaskOp.getNode())) in match()
101 if (auto VLenPos = ISD::getVPExplicitVectorLengthIdx(VPOpcode)) in match()
112 unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); in getNode()
113 assert(ISD::getVPMaskIdx(VPOpcode) == 1 && in getNode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp270 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
271 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
273 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && in getArithmeticInstrCost()
323 ISD = X86ISD::PMULUDQ; in getArithmeticInstrCost()
328 if (ISD == ISD::MUL && Op2Info.isConstant() && in getArithmeticInstrCost()
342 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
352 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
364 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
366 if (ISD == ISD::UDIV) in getArithmeticInstrCost()
375 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp75 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
76 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
79 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
81 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
82 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
84 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
85 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
87 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
88 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
[all …]
H A DR600ISelLowering.cpp46 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
50 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
58 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
61 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
64 setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
87 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
88 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
89 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
92 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp457 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
461 case ISD::ATOMIC_SWAP: { in getOUTLINE_ATOMIC()
465 case ISD::ATOMIC_LOAD_ADD: { in getOUTLINE_ATOMIC()
469 case ISD::ATOMIC_LOAD_OR: { in getOUTLINE_ATOMIC()
473 case ISD::ATOMIC_LOAD_CLR: { in getOUTLINE_ATOMIC()
477 case ISD::ATOMIC_LOAD_XOR: { in getOUTLINE_ATOMIC()
507 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) in getSYNC()
508 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
509 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) in getSYNC()
510 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) in getSYNC()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h84 namespace ISD {
672 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
680 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
687 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
691 bool isUndef() const { return NodeType == ISD::UNDEF; }
699 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
700 NodeType == ISD::INTRINSIC_VOID) &&
709 case ISD::STRICT_FP16_TO_FP:
710 case ISD::STRICT_FP_TO_FP16:
711 case ISD::STRICT_BF16_TO_FP:
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp483 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
484 assert(ISD && "Invalid opcode"); in getCastInstrCost()
523 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
524 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
525 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
526 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
527 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
528 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
529 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
530 {ISD::ZERO_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp159 static SDValue handleCMSEValue(const SDValue &Value, const ISD::InputArg &Arg, in handleCMSEValue()
163 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, Arg.ArgVT, Value); in handleCMSEValue()
165 DAG.getNode(Arg.Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, in handleCMSEValue()
172 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
173 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
175 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
176 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
181 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
182 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
183 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp61 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
62 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
66 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
67 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
68 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
75 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
76 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
77 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp235 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, XLenVT, in RISCVTargetLowering()
238 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i32, in RISCVTargetLowering()
242 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); in RISCVTargetLowering()
244 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in RISCVTargetLowering()
245 setOperationAction(ISD::BR_CC, XLenVT, Expand); in RISCVTargetLowering()
247 setOperationAction(ISD in RISCVTargetLowering()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp110 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in initializeHVXLowering()
111 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in initializeHVXLowering()
112 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in initializeHVXLowering()
113 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom); in initializeHVXLowering()
114 setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); in initializeHVXLowering()
115 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in initializeHVXLowering()
116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
118 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in initializeHVXLowering()
127 setOperationAction(ISD in initializeHVXLowering()
[all...]
H A DHexagonISelLowering.cpp142 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_SkipOdd()
175 SDValue Chain, ISD::ArgFlagsTy Flags, in CreateCopyOfByValArgument()
187 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
197 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
203 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
213 // Analyze return values of ISD::RET in LowerReturn()
237 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
240 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
243 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
344 /// LowerCallResult - Lower the result values of an ISD
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp46 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
59 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Split_64()
85 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Ret_Split_64()
109 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in Analyze_CC_Sparc64_Full()
159 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in Analyze_CC_Sparc64_Half()
196 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
203 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
210 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in RetCC_Sparc64_Full()
217 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in RetCC_Sparc64_Half()
237 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp63 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
64 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
76 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote); in M68kTargetLowering()
77 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal); in M68kTargetLowering()
79 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal); in M68kTargetLowering()
81 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall); in M68kTargetLowering()
82 setOperationAction(ISD::MUL, MVT::i64, LibCall); in M68kTargetLowering()
85 {ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp286 case ISD::SPLAT_VECTOR: in isZeroingInactiveLanes()
290 case ISD::INTRINSIC_WO_CHAIN: in isZeroingInactiveLanes()
351 if (Disc->getOpcode() == ISD::INTRINSIC_WO_CHAIN && in extractPtrauthBlendDiscriminators()
392 setOperationAction(ISD::LOAD, MVT::i64x8, Custom); in AArch64TargetLowering()
393 setOperationAction(ISD::STORE, MVT::i64x8, Custom); in AArch64TargetLowering()
465 setOperationPromotedToType(ISD::LOAD, MVT::aarch64svcount, MVT::nxv16i1); in AArch64TargetLowering()
466 setOperationPromotedToType(ISD::STORE, MVT::aarch64svcount, MVT::nxv16i1); in AArch64TargetLowering()
468 setOperationAction(ISD::SELECT, MVT::aarch64svcount, Custom); in AArch64TargetLowering()
469 setOperationAction(ISD::SELECT_CC, MVT::aarch64svcount, Expand); in AArch64TargetLowering()
476 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp89 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
90 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
95 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
96 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
103 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
104 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
108 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
109 setOperationAction(ISD::GlobalTLSAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
110 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom); in WebAssemblyTargetLowering()
111 setOperationAction(ISD::JumpTable, MVTPtr, Custom); in WebAssemblyTargetLowering()
[all …]

12345678910