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Searched refs:ISD (Results 1 – 25 of 245) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp61 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
83 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
85 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
86 case ISD::MEMBARRIER: return "MemBarrier"; in getOperationName()
87 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
88 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
89 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; in getOperationName()
90 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
91 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
92 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
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H A DLegalizeVectorOps.cpp298 case ISD::LOAD: { in LegalizeOp()
300 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
302 if (LoadedVT.isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
306 case ISD::STORE: { in LegalizeOp()
314 case ISD::MERGE_VALUES: in LegalizeOp()
322 case ISD::STRICT_##DAGN: in LegalizeOp()
325 if (Op.getOpcode() == ISD::STRICT_SINT_TO_FP || in LegalizeOp()
326 Op.getOpcode() == ISD::STRICT_UINT_TO_FP) in LegalizeOp()
328 if (Op.getOpcode() == ISD::STRICT_FSETCC || in LegalizeOp()
329 Op.getOpcode() == ISD::STRICT_FSETCCS) { in LegalizeOp()
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H A DLegalizeDAG.cpp351 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
367 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
404 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
422 if (!ISD::isNormalStore(ST)) in OptimizeFloatStore()
440 if (Value.getOpcode() == ISD::TargetConstantFP) in OptimizeFloatStore()
480 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); in OptimizeFloatStore()
505 switch (TLI.getOperationAction(ISD::STORE, VT)) { in LegalizeStoreOps()
529 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT); in LegalizeStoreOps()
532 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
587 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
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H A DLegalizeIntegerTypes.cpp58 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
59 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
60 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
61 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
62 case ISD::VP_BITREVERSE: in PromoteIntegerResult()
63 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
64 case ISD::VP_BSWAP: in PromoteIntegerResult()
65 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
66 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
67 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
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H A DLegalizeVectorTypes.cpp56 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
57 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
58 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
59 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
60 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
61 case ISD::AssertZext: in ScalarizeVectorResult()
62 case ISD::AssertSext: in ScalarizeVectorResult()
63 case ISD::FPOWI: in ScalarizeVectorResult()
64 case ISD::AssertNoFPClass: in ScalarizeVectorResult()
67 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
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H A DTargetLowering.cpp106 if (Value->getOpcode() == ISD::AssertZext) in parametersInCSRMatch()
108 if (Value->getOpcode() != ISD::CopyFromReg) in parametersInCSRMatch()
257 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
261 isOperationLegalOrCustom(ISD::STORE, MVT::f64) && in findOptimalMemOpLowering()
307 ISD::CondCode &CCCode, in softenSetCCOperands()
317 ISD::CondCode &CCCode, in softenSetCCOperands()
333 case ISD::SETEQ: in softenSetCCOperands()
334 case ISD::SETOEQ: in softenSetCCOperands()
339 case ISD::SETNE: in softenSetCCOperands()
340 case ISD::SETUNE: in softenSetCCOperands()
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H A DLegalizeFloatTypes.cpp64 case ISD::EXTRACT_ELEMENT: R = SoftenFloatRes_EXTRACT_ELEMENT(N); break; in SoftenFloatResult()
65 case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break; in SoftenFloatResult()
66 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
67 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult()
68 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
69 case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N); break; in SoftenFloatResult()
70 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
72 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
73 case ISD::STRICT_FMINNUM: in SoftenFloatResult()
74 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
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H A DDAGCombiner.cpp277 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
282 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
404 ISD::CondCode CC);
596 SDValue N2, SDValue N3, ISD::CondCode CC,
600 ISD::CondCode CC);
603 SDValue N2, SDValue N3, ISD::CondCode CC);
611 SDValue False, ISD::CondCode CC, const SDLoc &DL);
614 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
729 case ISD::Constant: in getStoreSource()
730 case ISD::ConstantFP: in getStoreSource()
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H A DSelectionDAG.cpp151 bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { in isConstantSplatVector()
152 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
182 bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllOnes()
184 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllOnes()
187 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllOnes()
192 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllOnes()
228 bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllZeros()
230 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllZeros()
233 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllZeros()
238 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllZeros()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp269 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
270 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
272 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && in getArithmeticInstrCost()
322 ISD = X86ISD::PMULUDQ; in getArithmeticInstrCost()
327 if (ISD == ISD::MUL && Op2Info.isConstant() && in getArithmeticInstrCost()
341 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
351 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
363 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
365 if (ISD == ISD::UDIV) in getArithmeticInstrCost()
374 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp75 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
76 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
79 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
81 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
82 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
84 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
85 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
87 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
88 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
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H A DR600ISelLowering.cpp45 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
49 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
57 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
60 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
63 setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
86 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
87 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
88 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
91 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
94 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp492 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
496 case ISD::ATOMIC_SWAP: { in getOUTLINE_ATOMIC()
500 case ISD::ATOMIC_LOAD_ADD: { in getOUTLINE_ATOMIC()
504 case ISD::ATOMIC_LOAD_OR: { in getOUTLINE_ATOMIC()
508 case ISD::ATOMIC_LOAD_CLR: { in getOUTLINE_ATOMIC()
512 case ISD::ATOMIC_LOAD_XOR: { in getOUTLINE_ATOMIC()
542 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) in getSYNC()
543 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
544 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) in getSYNC()
545 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) in getSYNC()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h85 namespace ISD {
696 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
700 return NodeType == ISD::UNDEF || NodeType == ISD::POISON;
705 return NodeType == ISD::ADD || NodeType == ISD::PTRADD;
716 case ISD::STRICT_FP16_TO_FP:
717 case ISD::STRICT_FP_TO_FP16:
718 case ISD::STRICT_BF16_TO_FP:
719 case ISD::STRICT_FP_TO_BF16:
721 case ISD::STRICT_##DAGN:
732 case ISD::AssertAlign:
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp79 case ISD::FADD: in hasNativeBF16Support()
80 case ISD::FMUL: in hasNativeBF16Support()
81 case ISD::FSUB: in hasNativeBF16Support()
82 case ISD::SELECT: in hasNativeBF16Support()
83 case ISD::SELECT_CC: in hasNativeBF16Support()
84 case ISD::SETCC: in hasNativeBF16Support()
85 case ISD::FEXP2: in hasNativeBF16Support()
86 case ISD::FCEIL: in hasNativeBF16Support()
87 case ISD::FFLOOR: in hasNativeBF16Support()
88 case ISD::FNEARBYINT: in hasNativeBF16Support()
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H A DNVPTXISelLowering.cpp543 case ISD::FMINNUM: in NVPTXTargetLowering()
544 case ISD::FMAXNUM: in NVPTXTargetLowering()
545 case ISD::FMAXNUM_IEEE: in NVPTXTargetLowering()
546 case ISD::FMINNUM_IEEE: in NVPTXTargetLowering()
547 case ISD::FMAXIMUM: in NVPTXTargetLowering()
548 case ISD::FMINIMUM: in NVPTXTargetLowering()
551 case ISD::FEXP2: in NVPTXTargetLowering()
570 case ISD::ADD: in NVPTXTargetLowering()
571 case ISD::SMAX: in NVPTXTargetLowering()
572 case ISD::SMIN: in NVPTXTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp503 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
504 assert(ISD && "Invalid opcode"); in getCastInstrCost()
543 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
544 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
545 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
546 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
547 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
548 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
549 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
550 {ISD::ZERO_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp110 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in initializeHVXLowering()
111 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in initializeHVXLowering()
112 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in initializeHVXLowering()
113 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom); in initializeHVXLowering()
114 setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); in initializeHVXLowering()
115 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in initializeHVXLowering()
116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
118 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in initializeHVXLowering()
121 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom); in initializeHVXLowering()
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H A DHexagonISelLowering.cpp140 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_SkipOdd()
248 SDValue Chain, ISD::ArgFlagsTy Flags, in CreateCopyOfByValArgument()
260 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
276 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
310 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
313 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
316 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
421 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
477 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
479 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp76 setOperationAction(ISD::Constant, MVT::i32, Custom); in XtensaTargetLowering()
77 setOperationAction(ISD::Constant, MVT::i64, Expand); in XtensaTargetLowering()
78 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); in XtensaTargetLowering()
79 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); in XtensaTargetLowering()
83 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in XtensaTargetLowering()
84 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::i8, MVT::i16}, in XtensaTargetLowering()
87 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in XtensaTargetLowering()
88 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in XtensaTargetLowering()
89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
90 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp286 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, XLenVT, in RISCVTargetLowering()
289 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i32, in RISCVTargetLowering()
293 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Custom); in RISCVTargetLowering()
295 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in RISCVTargetLowering()
296 setOperationAction(ISD::BR_CC, XLenVT, Expand); in RISCVTargetLowering()
297 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in RISCVTargetLowering()
298 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); in RISCVTargetLowering()
300 setCondCodeAction(ISD::SETGT, XLenVT, Custom); in RISCVTargetLowering()
301 setCondCodeAction(ISD::SETGE, XLenVT, Expand); in RISCVTargetLowering()
302 setCondCodeAction(ISD::SETUGT, XLenVT, Custom); in RISCVTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
69 inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) { in intCondCode2Icc()
73 case ISD::SETEQ: in intCondCode2Icc()
75 case ISD::SETNE: in intCondCode2Icc()
77 case ISD::SETLT: in intCondCode2Icc()
79 case ISD::SETGT: in intCondCode2Icc()
81 case ISD::SETLE: in intCondCode2Icc()
83 case ISD::SETGE: in intCondCode2Icc()
85 case ISD::SETULT: in intCondCode2Icc()
87 case ISD::SETULE: in intCondCode2Icc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp65 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
66 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
67 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
78 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote); in M68kTargetLowering()
79 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal); in M68kTargetLowering()
81 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal); in M68kTargetLowering()
83 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall); in M68kTargetLowering()
84 setOperationAction(ISD::MUL, MVT::i64, LibCall); in M68kTargetLowering()
87 {ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
88 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp87 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
88 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
93 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
94 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
98 setOperationAction(ISD::LOAD, MVT::v8f16, Custom); in WebAssemblyTargetLowering()
99 setOperationAction(ISD::STORE, MVT::v8f16, Custom); in WebAssemblyTargetLowering()
105 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
106 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
110 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
111 setOperationAction(ISD::GlobalTLSAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp293 case ISD::SPLAT_VECTOR: in isZeroingInactiveLanes()
294 case ISD::GET_ACTIVE_LANE_MASK: in isZeroingInactiveLanes()
298 case ISD::INTRINSIC_WO_CHAIN: in isZeroingInactiveLanes()
359 if (Disc->getOpcode() == ISD::INTRINSIC_WO_CHAIN && in extractPtrauthBlendDiscriminators()
400 setOperationAction(ISD::LOAD, MVT::i64x8, Custom); in AArch64TargetLowering()
401 setOperationAction(ISD::STORE, MVT::i64x8, Custom); in AArch64TargetLowering()
474 setOperationPromotedToType(ISD::LOAD, MVT::aarch64svcount, MVT::nxv16i1); in AArch64TargetLowering()
475 setOperationPromotedToType(ISD::STORE, MVT::aarch64svcount, MVT::nxv16i1); in AArch64TargetLowering()
477 setOperationAction(ISD::SELECT, MVT::aarch64svcount, Custom); in AArch64TargetLowering()
478 setOperationAction(ISD::SELECT_CC, MVT::aarch64svcount, Expand); in AArch64TargetLowering()
[all …]

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