Lines Matching refs:ISD
46 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
50 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
58 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
61 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
64 setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
87 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
88 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
89 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
92 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
97 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
99 setOperationAction(ISD::BR_CC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
100 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
102 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
104 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in R600TargetLowering()
107 setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::i32}, Custom); in R600TargetLowering()
109 setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
110 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
113 setOperationAction(ISD::SELECT, {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
119 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
122 setOperationAction(ISD::USUBO, MVT::i32, Custom); in R600TargetLowering()
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
128 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i1, MVT::v4i1}, Expand); in R600TargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i8, MVT::v4i8}, Expand); in R600TargetLowering()
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
136 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i16, MVT::v4i16}, Expand); in R600TargetLowering()
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
139 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i32, MVT::v4i32}, Expand); in R600TargetLowering()
141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
143 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
145 setOperationAction(ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
148 setOperationAction(ISD::INSERT_VECTOR_ELT, in R600TargetLowering()
153 setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, MVT::i32, in R600TargetLowering()
157 setOperationAction(ISD::FMA, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
160 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
164 setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
167 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in R600TargetLowering()
170 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in R600TargetLowering()
173 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
176 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
183 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in R600TargetLowering()
184 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom); in R600TargetLowering()
188 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
193 setOperationAction({ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE}, MVT::i32, Expand); in R600TargetLowering()
196 setOperationAction({ISD::INTRINSIC_VOID, ISD::INTRINSIC_WO_CHAIN}, MVT::Other, in R600TargetLowering()
201 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
202 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD}); in R600TargetLowering()
401 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
402 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
403 case ISD::SHL_PARTS: in LowerOperation()
404 case ISD::SRA_PARTS: in LowerOperation()
405 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); in LowerOperation()
406 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
407 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW); in LowerOperation()
408 case ISD::FCOS: in LowerOperation()
409 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
410 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
411 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
412 case ISD::LOAD: { in LowerOperation()
420 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
421 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG); in LowerOperation()
422 case ISD::FrameIndex: return lowerFrameIndex(Op, DAG); in LowerOperation()
423 case ISD::ADDRSPACECAST: in LowerOperation()
425 case ISD::INTRINSIC_VOID: { in LowerOperation()
450 case ISD::INTRINSIC_WO_CHAIN: { in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
508 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
586 case ISD::FP_TO_UINT: in ReplaceNodeResults()
595 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
606 case ISD::SDIVREM: { in ReplaceNodeResults()
613 case ISD::UDIVREM: { in ReplaceNodeResults()
629 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
647 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
663 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
692 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
693 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
698 case ISD::FCOS: in LowerTrig()
701 case ISD::FSIN: in LowerTrig()
708 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
713 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
734 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
739 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
745 ISD::SETCC, in lowerFP_TO_UINT()
749 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
755 ISD::SETCC, in lowerFP_TO_SINT()
759 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
833 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
834 ISD::CondCode InverseCC = ISD::getSetCCInverse(CCOpcode, CompareVT); in LowerSELECT_CC()
839 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC); in LowerSELECT_CC()
851 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
866 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
868 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
874 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT); in LowerSELECT_CC()
875 CCSwapped = ISD::getSetCCSwappedOperands(CCInv); in LowerSELECT_CC()
886 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
892 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
893 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
897 case ISD::SETONE: in LowerSELECT_CC()
898 case ISD::SETUNE: in LowerSELECT_CC()
899 case ISD::SETNE: in LowerSELECT_CC()
900 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT); in LowerSELECT_CC()
908 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
912 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
932 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
934 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
937 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
981 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1043 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1048 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1059 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1063 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1068 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1075 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1079 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1086 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1089 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1146 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1163 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr, in LowerSTORE()
1165 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1169 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1172 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1173 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1265 ISD::LoadExtType ExtType = Load->getExtensionType(); in lowerPrivateExtLoad()
1275 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1280 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1289 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1293 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1297 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1302 if (ExtType == ISD::SEXTLOAD) { // ... ones. in lowerPrivateExtLoad()
1304 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1321 ISD::LoadExtType ExtType = LoadNode->getExtensionType(); in LowerLOAD()
1324 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1344 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) || in LowerLOAD()
1345 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
1354 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1361 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1379 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) { in LowerLOAD()
1382 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT, in LowerLOAD()
1384 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1398 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1456 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
1462 SmallVector<ISD::InputArg, 8> LocalIns; in LowerFormalArguments()
1472 const ISD::InputArg &In = Ins[i]; in LowerFormalArguments()
1494 ISD::LoadExtType Ext = ISD::NON_EXTLOAD; in LowerFormalArguments()
1500 Ext = ISD::SEXTLOAD; in LowerFormalArguments()
1512 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1569 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in CompactSwizzlableVector()
1614 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in ReorganizeVector()
1619 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1627 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1675 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode)) in constBufferLoad()
1690 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in constBufferLoad()
1702 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1723 case ISD::FP_ROUND: { in PerformDAGCombine()
1725 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1726 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
1737 case ISD::FP_TO_SINT: { in PerformDAGCombine()
1739 if (FNeg.getOpcode() != ISD::FNEG) { in PerformDAGCombine()
1743 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1751 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1761 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
1773 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
1785 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1802 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1803 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
1813 case ISD::EXTRACT_VECTOR_ELT: { in PerformDAGCombine()
1815 if (Arg.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1821 if (Arg.getOpcode() == ISD::BITCAST && in PerformDAGCombine()
1822 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in PerformDAGCombine()
1827 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
1834 case ISD::SELECT_CC: { in PerformDAGCombine()
1845 if (LHS.getOpcode() != ISD::SELECT_CC) { in PerformDAGCombine()
1852 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in PerformDAGCombine()
1862 case ISD::SETNE: return LHS; in PerformDAGCombine()
1863 case ISD::SETEQ: { in PerformDAGCombine()
1864 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get(); in PerformDAGCombine()
1865 LHSCC = ISD::getSetCCInverse(LHSCC, LHS.getOperand(0).getValueType()); in PerformDAGCombine()
1882 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
1900 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
1928 case ISD::LOAD: { in PerformDAGCombine()