Lines Matching refs:ISD
63 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
64 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
76 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote); in M68kTargetLowering()
77 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal); in M68kTargetLowering()
79 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal); in M68kTargetLowering()
81 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall); in M68kTargetLowering()
82 setOperationAction(ISD::MUL, MVT::i64, LibCall); in M68kTargetLowering()
85 {ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
97 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
103 for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) in M68kTargetLowering()
108 setOperationAction(ISD::ADDC, VT, Custom); in M68kTargetLowering()
109 setOperationAction(ISD::ADDE, VT, Custom); in M68kTargetLowering()
110 setOperationAction(ISD::SUBC, VT, Custom); in M68kTargetLowering()
111 setOperationAction(ISD::SUBE, VT, Custom); in M68kTargetLowering()
116 setOperationAction(ISD::SADDO, VT, Custom); in M68kTargetLowering()
117 setOperationAction(ISD::UADDO, VT, Custom); in M68kTargetLowering()
118 setOperationAction(ISD::SSUBO, VT, Custom); in M68kTargetLowering()
119 setOperationAction(ISD::USUBO, VT, Custom); in M68kTargetLowering()
122 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in M68kTargetLowering()
123 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in M68kTargetLowering()
126 setOperationAction(ISD::BR_CC, VT, Expand); in M68kTargetLowering()
127 setOperationAction(ISD::SELECT, VT, Custom); in M68kTargetLowering()
128 setOperationAction(ISD::SELECT_CC, VT, Expand); in M68kTargetLowering()
129 setOperationAction(ISD::SETCC, VT, Custom); in M68kTargetLowering()
130 setOperationAction(ISD::SETCCCARRY, VT, Custom); in M68kTargetLowering()
134 setOperationAction(ISD::BSWAP, VT, Expand); in M68kTargetLowering()
135 setOperationAction(ISD::CTTZ, VT, Expand); in M68kTargetLowering()
136 setOperationAction(ISD::CTLZ, VT, Expand); in M68kTargetLowering()
137 setOperationAction(ISD::CTPOP, VT, Expand); in M68kTargetLowering()
140 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in M68kTargetLowering()
141 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in M68kTargetLowering()
142 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in M68kTargetLowering()
143 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in M68kTargetLowering()
144 setOperationAction(ISD::ExternalSymbol, MVT::i32, Custom); in M68kTargetLowering()
145 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in M68kTargetLowering()
147 setOperationAction(ISD::VASTART, MVT::Other, Custom); in M68kTargetLowering()
148 setOperationAction(ISD::VAEND, MVT::Other, Expand); in M68kTargetLowering()
149 setOperationAction(ISD::VAARG, MVT::Other, Expand); in M68kTargetLowering()
150 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in M68kTargetLowering()
152 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in M68kTargetLowering()
153 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in M68kTargetLowering()
155 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom); in M68kTargetLowering()
162 setOperationAction(ISD::ATOMIC_CMP_SWAP, {MVT::i8, MVT::i16, MVT::i32}, in M68kTargetLowering()
165 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); in M68kTargetLowering()
172 ISD::ATOMIC_LOAD_ADD, in M68kTargetLowering()
173 ISD::ATOMIC_LOAD_SUB, in M68kTargetLowering()
174 ISD::ATOMIC_LOAD_AND, in M68kTargetLowering()
175 ISD::ATOMIC_LOAD_OR, in M68kTargetLowering()
176 ISD::ATOMIC_LOAD_XOR, in M68kTargetLowering()
177 ISD::ATOMIC_LOAD_NAND, in M68kTargetLowering()
178 ISD::ATOMIC_LOAD_MIN, in M68kTargetLowering()
179 ISD::ATOMIC_LOAD_MAX, in M68kTargetLowering()
180 ISD::ATOMIC_LOAD_UMIN, in M68kTargetLowering()
181 ISD::ATOMIC_LOAD_UMAX, in M68kTargetLowering()
182 ISD::ATOMIC_SWAP, in M68kTargetLowering()
234 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { in callIsStructReturn()
238 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; in callIsStructReturn()
248 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { in argsAreStructReturn()
252 const ISD::ArgFlagsTy &Flags = Ins[0].Flags; in argsAreStructReturn()
264 SDValue Chain, ISD::ArgFlagsTy Flags, in CreateCopyOfByValArgument()
297 ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, in MatchingStackOffset()
306 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
310 if (Op == ISD::TRUNCATE) { in MatchingStackOffset()
312 if (TruncInput.getOpcode() == ISD::AssertZext && in MatchingStackOffset()
323 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
355 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { in MatchingStackOffset()
431 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerMemArgument()
437 ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags; in LowerMemArgument()
494 return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val) in LowerMemArgument()
503 ISD::ArgFlagsTy Flags) const { in LowerMemOpCallTo()
506 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
524 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
526 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
639 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
657 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
660 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
663 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
694 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall()
729 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
746 Source = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerCall()
760 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2); in LowerCall()
777 if (Callee->getOpcode() == ISD::GlobalAddress) { in LowerCall()
885 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCallResult()
905 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
920 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
961 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
964 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
971 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
1004 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); in LowerFormalArguments()
1064 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn()
1073 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
1100 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1102 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1105 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1107 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1226 const SmallVectorImpl<ISD::OutputArg> &Outs, in IsEligibleForTailCallOptimization()
1228 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const { in IsEligibleForTailCallOptimization()
1309 ISD::ArgFlagsTy Flags = Outs[i].Flags; in IsEligibleForTailCallOptimization()
1382 case ISD::SADDO: in LowerOperation()
1383 case ISD::UADDO: in LowerOperation()
1384 case ISD::SSUBO: in LowerOperation()
1385 case ISD::USUBO: in LowerOperation()
1386 case ISD::SMULO: in LowerOperation()
1387 case ISD::UMULO: in LowerOperation()
1389 case ISD::SETCC: in LowerOperation()
1391 case ISD::SETCCCARRY: in LowerOperation()
1393 case ISD::SELECT: in LowerOperation()
1395 case ISD::BRCOND: in LowerOperation()
1397 case ISD::ADDC: in LowerOperation()
1398 case ISD::ADDE: in LowerOperation()
1399 case ISD::SUBC: in LowerOperation()
1400 case ISD::SUBE: in LowerOperation()
1402 case ISD::ConstantPool: in LowerOperation()
1404 case ISD::GlobalAddress: in LowerOperation()
1406 case ISD::ExternalSymbol: in LowerOperation()
1408 case ISD::BlockAddress: in LowerOperation()
1410 case ISD::JumpTable: in LowerOperation()
1412 case ISD::VASTART: in LowerOperation()
1414 case ISD::DYNAMIC_STACKALLOC: in LowerOperation()
1416 case ISD::SHL_PARTS: in LowerOperation()
1418 case ISD::SRA_PARTS: in LowerOperation()
1420 case ISD::SRL_PARTS: in LowerOperation()
1422 case ISD::ATOMIC_FENCE: in LowerOperation()
1424 case ISD::GlobalTLSAddress: in LowerOperation()
1450 SDValue Arg = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, GOT, TGA); in getTLSGetAddr()
1478 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Addr); in LowerTLSLocalDynamic()
1488 SDValue Addr = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, GOT); in LowerTLSInitialExec()
1493 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, Offset, Tp); in LowerTLSInitialExec()
1502 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Tp); in LowerTLSLocalExec()
1538 case ISD::UADDO: in isOverflowArithmetic()
1539 case ISD::SADDO: in isOverflowArithmetic()
1540 case ISD::USUBO: in isOverflowArithmetic()
1541 case ISD::SSUBO: in isOverflowArithmetic()
1542 case ISD::UMULO: in isOverflowArithmetic()
1543 case ISD::SMULO: in isOverflowArithmetic()
1569 TruncOp = ISD::TRUNCATE; in lowerOverflowArithmetic()
1578 case ISD::SADDO: in lowerOverflowArithmetic()
1582 case ISD::UADDO: in lowerOverflowArithmetic()
1586 case ISD::SSUBO: in lowerOverflowArithmetic()
1590 case ISD::USUBO: in lowerOverflowArithmetic()
1594 case ISD::UMULO: in lowerOverflowArithmetic()
1595 PromoteMULO(ISD::ZERO_EXTEND); in lowerOverflowArithmetic()
1597 BaseOp = NoOverflow ? ISD::MUL : M68kISD::UMUL; in lowerOverflowArithmetic()
1600 case ISD::SMULO: in lowerOverflowArithmetic()
1601 PromoteMULO(ISD::SIGN_EXTEND); in lowerOverflowArithmetic()
1603 BaseOp = NoOverflow ? ISD::MUL : M68kISD::SMUL; in lowerOverflowArithmetic()
1648 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Overflow); in LowerXALUO()
1653 static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, in getBitTestCondition()
1659 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src); in getBitTestCondition()
1664 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo); in getBitTestCondition()
1669 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition()
1675 static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, in LowerAndToBTST()
1679 if (Op0.getOpcode() == ISD::TRUNCATE) in LowerAndToBTST()
1681 if (Op1.getOpcode() == ISD::TRUNCATE) in LowerAndToBTST()
1685 if (Op1.getOpcode() == ISD::SHL) in LowerAndToBTST()
1687 if (Op0.getOpcode() == ISD::SHL) { in LowerAndToBTST()
1705 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { in LowerAndToBTST()
1723 static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode) { in TranslateIntegerM68kCC()
1727 case ISD::SETEQ: in TranslateIntegerM68kCC()
1729 case ISD::SETGT: in TranslateIntegerM68kCC()
1731 case ISD::SETGE: in TranslateIntegerM68kCC()
1733 case ISD::SETLT: in TranslateIntegerM68kCC()
1735 case ISD::SETLE: in TranslateIntegerM68kCC()
1737 case ISD::SETNE: in TranslateIntegerM68kCC()
1739 case ISD::SETULT: in TranslateIntegerM68kCC()
1741 case ISD::SETUGE: in TranslateIntegerM68kCC()
1743 case ISD::SETUGT: in TranslateIntegerM68kCC()
1745 case ISD::SETULE: in TranslateIntegerM68kCC()
1753 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, in TranslateM68kCC()
1758 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnes()) { in TranslateM68kCC()
1763 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) { in TranslateM68kCC()
1767 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1780 if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) { in TranslateM68kCC()
1788 case ISD::SETOLT: in TranslateM68kCC()
1789 case ISD::SETOLE: in TranslateM68kCC()
1790 case ISD::SETUGT: in TranslateM68kCC()
1791 case ISD::SETUGE: in TranslateM68kCC()
1805 case ISD::SETUEQ: in TranslateM68kCC()
1806 case ISD::SETEQ: in TranslateM68kCC()
1808 case ISD::SETOLT: // flipped in TranslateM68kCC()
1809 case ISD::SETOGT: in TranslateM68kCC()
1810 case ISD::SETGT: in TranslateM68kCC()
1812 case ISD::SETOLE: // flipped in TranslateM68kCC()
1813 case ISD::SETOGE: in TranslateM68kCC()
1814 case ISD::SETGE: in TranslateM68kCC()
1816 case ISD::SETUGT: // flipped in TranslateM68kCC()
1817 case ISD::SETULT: in TranslateM68kCC()
1818 case ISD::SETLT: in TranslateM68kCC()
1820 case ISD::SETUGE: // flipped in TranslateM68kCC()
1821 case ISD::SETULE: in TranslateM68kCC()
1822 case ISD::SETLE: in TranslateM68kCC()
1824 case ISD::SETONE: in TranslateM68kCC()
1825 case ISD::SETNE: in TranslateM68kCC()
1827 case ISD::SETOEQ: in TranslateM68kCC()
1828 case ISD::SETUNE: in TranslateM68kCC()
1834 static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, in LowerTruncateToBTST()
1837 assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 && in LowerTruncateToBTST()
1840 if (Op.getOperand(0).getOpcode() != ISD::SRL) in LowerTruncateToBTST()
1854 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { in hasNonFlagsUse()
1860 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && in hasNonFlagsUse()
1861 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) in hasNonFlagsUse()
1893 case ISD::ADD: in EmitTest()
1894 case ISD::SUB: in EmitTest()
1895 case ISD::MUL: in EmitTest()
1896 case ISD::SHL: { in EmitTest()
1924 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { in EmitTest()
1931 case ISD::ADD: in EmitTest()
1932 case ISD::SUB: in EmitTest()
1933 case ISD::AND: in EmitTest()
1934 case ISD::OR: in EmitTest()
1935 case ISD::XOR: { in EmitTest()
1946 case ISD::ADD: in EmitTest()
1950 case ISD::SHL: in EmitTest()
1951 case ISD::SRL: in EmitTest()
1963 APInt Mask = ArithOp.getOpcode() == ISD::SRL in EmitTest()
1968 Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0), in EmitTest()
1973 case ISD::AND: in EmitTest()
1989 case ISD::SUB: in EmitTest()
1990 case ISD::OR: in EmitTest()
1991 case ISD::XOR: in EmitTest()
1995 if (U->getOpcode() == ISD::STORE) in EmitTest()
2002 case ISD::SUB: in EmitTest()
2005 case ISD::XOR: in EmitTest()
2008 case ISD::AND: in EmitTest()
2011 case ISD::OR: in EmitTest()
2042 case ISD::ADD: in EmitTest()
2045 case ISD::SUB: in EmitTest()
2048 case ISD::AND: in EmitTest()
2051 case ISD::OR: in EmitTest()
2054 case ISD::XOR: in EmitTest()
2062 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0)); in EmitTest()
2063 SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1)); in EmitTest()
2118 isM68kCCUnsigned(M68kCC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in EmitCmp()
2132 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC, in LowerToBTST()
2135 if (Op.getOpcode() == ISD::AND) in LowerToBTST()
2137 if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1) in LowerToBTST()
2149 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
2157 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2160 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC); in LowerSETCC()
2168 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2174 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in LowerSETCC()
2183 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
2187 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2189 ISD::CondCode NewCC = ISD::GlobalISel::getSetCCInverse(CC, true); in LowerSETCC()
2193 SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1); in LowerSETCC()
2250 if (V.getOpcode() != ISD::TRUNCATE) in isTruncWithZeroHighBitsInput()
2268 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
2318 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); in LowerSELECT()
2324 if (Cond.getOpcode() == ISD::AND && in LowerSELECT()
2360 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { in LowerSELECT()
2361 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerSELECT()
2396 if (Op.getValueType() == MVT::i8 && Op1.getOpcode() == ISD::TRUNCATE && in LowerSELECT()
2397 Op2.getOpcode() == ISD::TRUNCATE) { in LowerSELECT()
2401 T1.getOpcode() != ISD::CopyFromReg && in LowerSELECT()
2402 T2.getOpcode() != ISD::CopyFromReg) { in LowerSELECT()
2405 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov); in LowerSELECT()
2431 if (Opc != ISD::OR && Opc != ISD::AND) in isAndOrOfSetCCs()
2442 if (Op.getOpcode() != ISD::XOR) in isXor1OfSetCC()
2459 if (Cond.getOpcode() == ISD::SETCC) { in LowerBRCOND()
2461 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && in LowerBRCOND()
2464 (Cond.getOperand(0).getOpcode() == ISD::SADDO || in LowerBRCOND()
2465 Cond.getOperand(0).getOpcode() == ISD::UADDO || in LowerBRCOND()
2466 Cond.getOperand(0).getOpcode() == ISD::SSUBO || in LowerBRCOND()
2467 Cond.getOperand(0).getOpcode() == ISD::USUBO)) { in LowerBRCOND()
2477 if (Cond.getOpcode() == ISD::AND && in LowerBRCOND()
2523 if (CondOpc == ISD::OR) { in LowerBRCOND()
2551 if (User->getOpcode() == ISD::BR) { in LowerBRCOND()
2590 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerBRCOND()
2622 case ISD::ADDC: in LowerADDC_ADDE_SUBC_SUBE()
2625 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
2629 case ISD::SUBC: in LowerADDC_ADDE_SUBC_SUBE()
2632 case ISD::SUBE: in LowerADDC_ADDE_SUBC_SUBE()
2672 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerConstantPool()
2702 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerExternalSymbol()
2737 DAG.getNode(ISD::ADD, DL, PtrVT, in LowerBlockAddress()
2768 DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalAddress()
2782 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result, in LowerGlobalAddress()
2820 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerJumpTable()
3371 return DAG.getNode(ISD::INLINEASM, SDLoc(Op), in LowerATOMICFENCE()
3417 Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
3419 Result = DAG.getNode(ISD::AND, DL, VT, Result, in LowerDYNAMIC_STACKALLOC()
3450 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftLeftParts()
3452 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftLeftParts()
3454 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in LowerShiftLeftParts()
3455 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in LowerShiftLeftParts()
3457 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt); in LowerShiftLeftParts()
3458 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in LowerShiftLeftParts()
3459 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); in LowerShiftLeftParts()
3460 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize); in LowerShiftLeftParts()
3463 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
3465 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); in LowerShiftLeftParts()
3466 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in LowerShiftLeftParts()
3495 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in LowerShiftRightParts()
3502 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftRightParts()
3504 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftRightParts()
3506 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in LowerShiftRightParts()
3507 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); in LowerShiftRightParts()
3509 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt); in LowerShiftRightParts()
3510 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi); in LowerShiftRightParts()
3515 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero; in LowerShiftRightParts()
3518 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()
3520 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); in LowerShiftRightParts()
3521 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in LowerShiftRightParts()
3542 while (Carry.getOpcode() == ISD::TRUNCATE || in combineCarryThroughADD()
3543 Carry.getOpcode() == ISD::ZERO_EXTEND || in combineCarryThroughADD()
3544 Carry.getOpcode() == ISD::SIGN_EXTEND || in combineCarryThroughADD()
3545 Carry.getOpcode() == ISD::ANY_EXTEND || in combineCarryThroughADD()
3546 (Carry.getOpcode() == ISD::AND && in combineCarryThroughADD()