Lines Matching refs:ISD
89 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
90 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
95 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
96 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
103 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
104 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
108 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
109 setOperationAction(ISD::GlobalTLSAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
110 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom); in WebAssemblyTargetLowering()
111 setOperationAction(ISD::JumpTable, MVTPtr, Custom); in WebAssemblyTargetLowering()
112 setOperationAction(ISD::BlockAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
113 setOperationAction(ISD::BRIND, MVT::Other, Custom); in WebAssemblyTargetLowering()
114 setOperationAction(ISD::CLEAR_CACHE, MVT::Other, Custom); in WebAssemblyTargetLowering()
118 setOperationAction(ISD::VASTART, MVT::Other, Custom); in WebAssemblyTargetLowering()
119 setOperationAction(ISD::VAARG, MVT::Other, Expand); in WebAssemblyTargetLowering()
120 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in WebAssemblyTargetLowering()
121 setOperationAction(ISD::VAEND, MVT::Other, Expand); in WebAssemblyTargetLowering()
125 setOperationAction(ISD::ConstantFP, T, Legal); in WebAssemblyTargetLowering()
127 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
128 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
132 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
136 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
137 ISD::FRINT, ISD::FROUNDEVEN}) in WebAssemblyTargetLowering()
140 setOperationAction(ISD::FMINIMUM, T, Legal); in WebAssemblyTargetLowering()
141 setOperationAction(ISD::FMAXIMUM, T, Legal); in WebAssemblyTargetLowering()
143 setOperationAction(ISD::FP16_TO_FP, T, Expand); in WebAssemblyTargetLowering()
144 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()
145 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand); in WebAssemblyTargetLowering()
150 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal); in WebAssemblyTargetLowering()
151 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal); in WebAssemblyTargetLowering()
156 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, in WebAssemblyTargetLowering()
157 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
158 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
167 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
174 setTargetDAGCombine(ISD::SETCC); in WebAssemblyTargetLowering()
177 setTargetDAGCombine(ISD::BITCAST); in WebAssemblyTargetLowering()
180 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
183 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}); in WebAssemblyTargetLowering()
187 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
188 ISD::EXTRACT_SUBVECTOR}); in WebAssemblyTargetLowering()
192 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
193 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
195 setTargetDAGCombine(ISD::TRUNCATE); in WebAssemblyTargetLowering()
198 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
204 setOperationAction(ISD::ABS, T, Legal); in WebAssemblyTargetLowering()
209 setOperationAction(ISD::BUILD_VECTOR, T, Custom); in WebAssemblyTargetLowering()
214 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
219 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in WebAssemblyTargetLowering()
222 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) in WebAssemblyTargetLowering()
227 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
233 setOperationAction(ISD::MUL, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
238 setOperationAction(ISD::SELECT_CC, T, Expand); in WebAssemblyTargetLowering()
242 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) in WebAssemblyTargetLowering()
247 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in WebAssemblyTargetLowering()
252 setOperationAction(ISD::CTPOP, MVT::v16i8, Legal); in WebAssemblyTargetLowering()
253 setOperationAction(ISD::CTLZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
254 setOperationAction(ISD::CTTZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
257 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}) in WebAssemblyTargetLowering()
262 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
263 ISD::FEXP, ISD::FEXP2}) in WebAssemblyTargetLowering()
268 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
273 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
278 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
283 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Custom); in WebAssemblyTargetLowering()
284 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Custom); in WebAssemblyTargetLowering()
290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in WebAssemblyTargetLowering()
295 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); in WebAssemblyTargetLowering()
298 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
301 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in WebAssemblyTargetLowering()
302 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in WebAssemblyTargetLowering()
303 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand); in WebAssemblyTargetLowering()
305 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in WebAssemblyTargetLowering()
306 setOperationAction(ISD::FrameIndex, MVT::i64, Custom); in WebAssemblyTargetLowering()
307 setOperationAction(ISD::CopyToReg, MVT::Other, Custom); in WebAssemblyTargetLowering()
311 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC}) in WebAssemblyTargetLowering()
315 setOperationAction(ISD::BR_JT, MVT::Other, Custom); in WebAssemblyTargetLowering()
322 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in WebAssemblyTargetLowering()
325 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
333 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
339 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in WebAssemblyTargetLowering()
344 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Legal); in WebAssemblyTargetLowering()
348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in WebAssemblyTargetLowering()
351 setOperationAction(ISD::TRAP, MVT::Other, Legal); in WebAssemblyTargetLowering()
352 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); in WebAssemblyTargetLowering()
355 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in WebAssemblyTargetLowering()
356 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); in WebAssemblyTargetLowering()
357 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in WebAssemblyTargetLowering()
418 if (Opc >= ISD::BUILTIN_OP_END) in shouldScalarizeBinop()
878 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
892 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
900 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
908 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
916 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
934 case ISD::INTRINSIC_WO_CHAIN: { in computeKnownBitsForTargetNode()
986 if (Op.getOpcode() == ISD::BUILD_VECTOR && TLO.LegalOps && TLO.LegalTys) in shouldSimplifyDemandedVectorElts()
1089 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
1090 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
1106 const ISD::OutputArg &Out = Outs[I]; in LowerCall()
1147 ISD::OutputArg Arg; in LowerCall()
1155 ISD::OutputArg Arg; in LowerCall()
1171 const ISD::OutputArg &Out = Outs[I]; in LowerCall()
1202 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode, in LowerCall()
1209 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerCall()
1214 if (Callee->getOpcode() == ISD::GlobalAddress) { in LowerCall()
1303 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
1311 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
1324 for (const ISD::OutputArg &Out : Outs) { in LowerReturn()
1341 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
1355 for (const ISD::InputArg &In : Ins) { in LowerFormalArguments()
1423 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1429 case ISD::SIGN_EXTEND_VECTOR_INREG: in ReplaceNodeResults()
1430 case ISD::ZERO_EXTEND_VECTOR_INREG: in ReplaceNodeResults()
1451 case ISD::FrameIndex: in LowerOperation()
1453 case ISD::GlobalAddress: in LowerOperation()
1455 case ISD::GlobalTLSAddress: in LowerOperation()
1457 case ISD::ExternalSymbol: in LowerOperation()
1459 case ISD::JumpTable: in LowerOperation()
1461 case ISD::BR_JT: in LowerOperation()
1463 case ISD::VASTART: in LowerOperation()
1465 case ISD::BlockAddress: in LowerOperation()
1466 case ISD::BRIND: in LowerOperation()
1469 case ISD::RETURNADDR: in LowerOperation()
1471 case ISD::FRAMEADDR: in LowerOperation()
1473 case ISD::CopyToReg: in LowerOperation()
1475 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1476 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
1478 case ISD::INTRINSIC_VOID: in LowerOperation()
1479 case ISD::INTRINSIC_WO_CHAIN: in LowerOperation()
1480 case ISD::INTRINSIC_W_CHAIN: in LowerOperation()
1482 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
1484 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
1485 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
1487 case ISD::BUILD_VECTOR: in LowerOperation()
1489 case ISD::VECTOR_SHUFFLE: in LowerOperation()
1491 case ISD::SETCC: in LowerOperation()
1493 case ISD::SHL: in LowerOperation()
1494 case ISD::SRA: in LowerOperation()
1495 case ISD::SRL: in LowerOperation()
1497 case ISD::FP_TO_SINT_SAT: in LowerOperation()
1498 case ISD::FP_TO_UINT_SAT: in LowerOperation()
1500 case ISD::LOAD: in LowerOperation()
1502 case ISD::STORE: in LowerOperation()
1504 case ISD::CTPOP: in LowerOperation()
1505 case ISD::CTLZ: in LowerOperation()
1506 case ISD::CTTZ: in LowerOperation()
1508 case ISD::CLEAR_CACHE: in LowerOperation()
1721 return DAG.getNode(ISD::ADD, DL, PtrVT, BaseAddr, SymOffset); in LowerGlobalTLSAddress()
1769 return DAG.getNode(ISD::ADD, DL, VT, BaseAddr, SymAddr); in LowerGlobalAddress()
1846 case ISD::INTRINSIC_VOID: in LowerIntrinsic()
1847 case ISD::INTRINSIC_W_CHAIN: in LowerIntrinsic()
1850 case ISD::INTRINSIC_WO_CHAIN: in LowerIntrinsic()
1875 return DAG.getNode(ISD::ADD, DL, PtrVT, BaseAddr, SymAddr); in LowerIntrinsic()
1890 bool isTarget = MaskIdx.getNode()->getOpcode() == ISD::TargetConstant; in LowerIntrinsic()
1913 if (Op.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerSIGN_EXTEND_INREG()
1938 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1940 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), NewExtract, in LowerSIGN_EXTEND_INREG()
1965 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerEXTEND_VECTOR_INREG()
1968 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerEXTEND_VECTOR_INREG()
1994 case ISD::SINT_TO_FP: in LowerConvertLow()
1997 case ISD::UINT_TO_FP: in LowerConvertLow()
2000 case ISD::FP_EXTEND: in LowerConvertLow()
2008 if (ExtractVector.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerConvertLow()
2073 return V.getOpcode() == ISD::Constant || V.getOpcode() == ISD::ConstantFP; in LowerBUILD_VECTOR()
2083 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2087 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG) in LowerBUILD_VECTOR()
2090 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2095 Index->getOperand(1)->getOpcode() != ISD::Constant || in LowerBUILD_VECTOR()
2106 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2292 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
2339 return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I], in LowerSETCC()
2381 DAG.getNode(ISD::AND, DL, MVT::i32, ShiftElements[i], Mask); in unrollVectorShift()
2383 if (ShiftOpcode == ISD::SRA) in unrollVectorShift()
2384 ShiftedValue = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, in unrollVectorShift()
2404 if (MaskOp.getOpcode() != ISD::AND) in LowerShift()
2410 if (!ISD::isConstantSplatVector(RHS.getNode(), MaskVal)) in LowerShift()
2413 if (ISD::isConstantSplatVector(RHS.getNode(), MaskVal) && in LowerShift()
2441 case ISD::SHL: in LowerShift()
2444 case ISD::SRA: in LowerShift()
2447 case ISD::SRL: in LowerShift()
2486 if (Bitcast.getOpcode() != ISD::BITCAST) in performVECTOR_SHUFFLECombine()
2508 assert(N->getOpcode() == ISD::UINT_TO_FP || in performVectorExtendToFPCombine()
2509 N->getOpcode() == ISD::SINT_TO_FP); in performVectorExtendToFPCombine()
2522 N->getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in performVectorExtendToFPCombine()
2530 assert(N->getOpcode() == ISD::SIGN_EXTEND || in performVectorExtendCombine()
2531 N->getOpcode() == ISD::ZERO_EXTEND); in performVectorExtendCombine()
2536 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorExtendCombine()
2563 bool IsSext = N->getOpcode() == ISD::SIGN_EXTEND; in performVectorExtendCombine()
2580 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2582 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine()
2584 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2603 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in performVectorTruncZeroCombine()
2620 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2621 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine()
2625 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2665 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2666 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine()
2669 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2713 if (Vec.getOpcode() == ISD::BUILD_VECTOR) in extractSubVector()
2718 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, VecIdx); in extractSubVector()
2772 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi); in truncateVectorWithNARROW()
2799 In = DAG.getNode(ISD::AND, DL, InVT, In, DAG.getConstant(Mask, DL, InVT)); in performTruncateCombine()
2820 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, in performBitcastCombine()
2836 ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get(); in performSETCCCombine()
2849 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && in performSETCCCombine()
2851 LHS->getOpcode() == ISD::BITCAST) { in performSETCCCombine()
2863 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, in performSETCCCombine()
2868 if ((isNullConstant(RHS) && (Cond == ISD::SETEQ)) || in performSETCCCombine()
2869 (isAllOnesConstant(RHS) && (Cond == ISD::SETNE))) { in performSETCCCombine()
2885 case ISD::BITCAST: in PerformDAGCombine()
2887 case ISD::SETCC: in PerformDAGCombine()
2889 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
2891 case ISD::SIGN_EXTEND: in PerformDAGCombine()
2892 case ISD::ZERO_EXTEND: in PerformDAGCombine()
2894 case ISD::UINT_TO_FP: in PerformDAGCombine()
2895 case ISD::SINT_TO_FP: in PerformDAGCombine()
2897 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
2898 case ISD::FP_TO_UINT_SAT: in PerformDAGCombine()
2899 case ISD::FP_ROUND: in PerformDAGCombine()
2900 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
2902 case ISD::TRUNCATE: in PerformDAGCombine()