Lines Matching refs:ISD
457 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
461 case ISD::ATOMIC_SWAP: { in getOUTLINE_ATOMIC()
465 case ISD::ATOMIC_LOAD_ADD: { in getOUTLINE_ATOMIC()
469 case ISD::ATOMIC_LOAD_OR: { in getOUTLINE_ATOMIC()
473 case ISD::ATOMIC_LOAD_CLR: { in getOUTLINE_ATOMIC()
477 case ISD::ATOMIC_LOAD_XOR: { in getOUTLINE_ATOMIC()
507 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) in getSYNC()
508 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
509 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) in getSYNC()
510 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) in getSYNC()
511 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) in getSYNC()
512 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) in getSYNC()
513 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) in getSYNC()
514 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) in getSYNC()
515 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) in getSYNC()
516 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) in getSYNC()
517 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) in getSYNC()
518 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) in getSYNC()
577 void RTLIB::initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs) { in initCmpLibcallCCs()
579 ISD::SETCC_INVALID); in initCmpLibcallCCs()
580 CmpLibcallCCs[RTLIB::OEQ_F32] = ISD::SETEQ; in initCmpLibcallCCs()
581 CmpLibcallCCs[RTLIB::OEQ_F64] = ISD::SETEQ; in initCmpLibcallCCs()
582 CmpLibcallCCs[RTLIB::OEQ_F128] = ISD::SETEQ; in initCmpLibcallCCs()
583 CmpLibcallCCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in initCmpLibcallCCs()
584 CmpLibcallCCs[RTLIB::UNE_F32] = ISD::SETNE; in initCmpLibcallCCs()
585 CmpLibcallCCs[RTLIB::UNE_F64] = ISD::SETNE; in initCmpLibcallCCs()
586 CmpLibcallCCs[RTLIB::UNE_F128] = ISD::SETNE; in initCmpLibcallCCs()
587 CmpLibcallCCs[RTLIB::UNE_PPCF128] = ISD::SETNE; in initCmpLibcallCCs()
588 CmpLibcallCCs[RTLIB::OGE_F32] = ISD::SETGE; in initCmpLibcallCCs()
589 CmpLibcallCCs[RTLIB::OGE_F64] = ISD::SETGE; in initCmpLibcallCCs()
590 CmpLibcallCCs[RTLIB::OGE_F128] = ISD::SETGE; in initCmpLibcallCCs()
591 CmpLibcallCCs[RTLIB::OGE_PPCF128] = ISD::SETGE; in initCmpLibcallCCs()
592 CmpLibcallCCs[RTLIB::OLT_F32] = ISD::SETLT; in initCmpLibcallCCs()
593 CmpLibcallCCs[RTLIB::OLT_F64] = ISD::SETLT; in initCmpLibcallCCs()
594 CmpLibcallCCs[RTLIB::OLT_F128] = ISD::SETLT; in initCmpLibcallCCs()
595 CmpLibcallCCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in initCmpLibcallCCs()
596 CmpLibcallCCs[RTLIB::OLE_F32] = ISD::SETLE; in initCmpLibcallCCs()
597 CmpLibcallCCs[RTLIB::OLE_F64] = ISD::SETLE; in initCmpLibcallCCs()
598 CmpLibcallCCs[RTLIB::OLE_F128] = ISD::SETLE; in initCmpLibcallCCs()
599 CmpLibcallCCs[RTLIB::OLE_PPCF128] = ISD::SETLE; in initCmpLibcallCCs()
600 CmpLibcallCCs[RTLIB::OGT_F32] = ISD::SETGT; in initCmpLibcallCCs()
601 CmpLibcallCCs[RTLIB::OGT_F64] = ISD::SETGT; in initCmpLibcallCCs()
602 CmpLibcallCCs[RTLIB::OGT_F128] = ISD::SETGT; in initCmpLibcallCCs()
603 CmpLibcallCCs[RTLIB::OGT_PPCF128] = ISD::SETGT; in initCmpLibcallCCs()
604 CmpLibcallCCs[RTLIB::UO_F32] = ISD::SETNE; in initCmpLibcallCCs()
605 CmpLibcallCCs[RTLIB::UO_F64] = ISD::SETNE; in initCmpLibcallCCs()
606 CmpLibcallCCs[RTLIB::UO_F128] = ISD::SETNE; in initCmpLibcallCCs()
607 CmpLibcallCCs[RTLIB::UO_PPCF128] = ISD::SETNE; in initCmpLibcallCCs()
662 setAtomicLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT, in initActions()
667 for (ISD::NodeType NT : enum_seq(ISD::DELETED_NODE, ISD::BUILTIN_OP_END, in initActions()
675 setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand); in initActions()
676 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand); in initActions()
679 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
680 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { in initActions()
692 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); in initActions()
693 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
700 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
701 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { in initActions()
709 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
712 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
713 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
714 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, in initActions()
715 ISD::FMINIMUM, ISD::FMAXIMUM, in initActions()
716 ISD::FMAD, ISD::SMIN, in initActions()
717 ISD::SMAX, ISD::UMIN, in initActions()
718 ISD::UMAX, ISD::ABS, in initActions()
719 ISD::FSHL, ISD::FSHR, in initActions()
720 ISD::SADDSAT, ISD::UADDSAT, in initActions()
721 ISD::SSUBSAT, ISD::USUBSAT, in initActions()
722 ISD::SSHLSAT, ISD::USHLSAT, in initActions()
723 ISD::SMULFIX, ISD::SMULFIXSAT, in initActions()
724 ISD::UMULFIX, ISD::UMULFIXSAT, in initActions()
725 ISD::SDIVFIX, ISD::SDIVFIXSAT, in initActions()
726 ISD::UDIVFIX, ISD::UDIVFIXSAT, in initActions()
727 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
728 ISD::IS_FPCLASS}, in initActions()
732 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
733 ISD::SMULO, ISD::UMULO}, in initActions()
737 setOperationAction({ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY, in initActions()
738 ISD::SADDO_CARRY, ISD::SSUBO_CARRY}, in initActions()
742 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
746 setOperationAction({ISD::UCMP, ISD::SCMP}, VT, Expand); in initActions()
750 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
754 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
757 setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in initActions()
760 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); in initActions()
763 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, in initActions()
769 {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, ISD::ANY_EXTEND_VECTOR_INREG, in initActions()
770 ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG, in initActions()
771 ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::FTAN, ISD::FACOS, in initActions()
772 ISD::FASIN, ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH}, in initActions()
777 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); in initActions()
781 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); in initActions()
785 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
786 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
787 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
788 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
789 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM, in initActions()
790 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL}, in initActions()
794 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
797 setOperationAction(ISD::VECTOR_COMPRESS, VT, Expand); in initActions()
801 setOperationAction(ISD::SDOPC, VT, Expand); in initActions()
805 setOperationAction(ISD::GET_FPENV, VT, Expand); in initActions()
806 setOperationAction(ISD::SET_FPENV, VT, Expand); in initActions()
807 setOperationAction(ISD::RESET_FPENV, VT, Expand); in initActions()
811 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); in initActions()
814 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); in initActions()
817 setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Expand); in initActions()
822 setOperationAction(ISD::ConstantFP, in initActions()
827 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in initActions()
828 ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, in initActions()
829 ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in initActions()
830 ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in initActions()
831 ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN, in initActions()
832 ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH}, in initActions()
835 setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH, in initActions()
836 ISD::FSINH, ISD::FTANH}, in initActions()
839 setOperationAction(ISD::TRAP, MVT::Other, Expand); in initActions()
843 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); in initActions()
845 setOperationAction(ISD::UBSANTRAP, MVT::Other, Expand); in initActions()
847 setOperationAction(ISD::GET_FPENV_MEM, MVT::Other, Expand); in initActions()
848 setOperationAction(ISD::SET_FPENV_MEM, MVT::Other, Expand); in initActions()
851 setOperationAction(ISD::GET_FPMODE, VT, Expand); in initActions()
852 setOperationAction(ISD::SET_FPMODE, VT, Expand); in initActions()
854 setOperationAction(ISD::RESET_FPMODE, MVT::Other, Expand); in initActions()
858 setOperationAction(ISD::CLEAR_CACHE, MVT::Other, LibCall); in initActions()
886 case ISD::SDIV: in canOpTrap()
887 case ISD::UDIV: in canOpTrap()
888 case ISD::SREM: in canOpTrap()
889 case ISD::UREM: in canOpTrap()
1640 SmallVectorImpl<ISD::OutputArg> &Outs, in GetReturnInfo()
1649 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in GetReturnInfo()
1652 ExtendKind = ISD::SIGN_EXTEND; in GetReturnInfo()
1654 ExtendKind = ISD::ZERO_EXTEND; in GetReturnInfo()
1656 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) in GetReturnInfo()
1665 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); in GetReturnInfo()
1676 ISD::ArgFlagsTy OutFlags = Flags; in GetReturnInfo()
1683 ISD::OutputArg(OutFlags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
1773 case FNeg: return ISD::FNEG; in InstructionOpcodeToISD()
1774 case Add: return ISD::ADD; in InstructionOpcodeToISD()
1775 case FAdd: return ISD::FADD; in InstructionOpcodeToISD()
1776 case Sub: return ISD::SUB; in InstructionOpcodeToISD()
1777 case FSub: return ISD::FSUB; in InstructionOpcodeToISD()
1778 case Mul: return ISD::MUL; in InstructionOpcodeToISD()
1779 case FMul: return ISD::FMUL; in InstructionOpcodeToISD()
1780 case UDiv: return ISD::UDIV; in InstructionOpcodeToISD()
1781 case SDiv: return ISD::SDIV; in InstructionOpcodeToISD()
1782 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
1783 case URem: return ISD::UREM; in InstructionOpcodeToISD()
1784 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
1785 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
1786 case Shl: return ISD::SHL; in InstructionOpcodeToISD()
1787 case LShr: return ISD::SRL; in InstructionOpcodeToISD()
1788 case AShr: return ISD::SRA; in InstructionOpcodeToISD()
1789 case And: return ISD::AND; in InstructionOpcodeToISD()
1790 case Or: return ISD::OR; in InstructionOpcodeToISD()
1791 case Xor: return ISD::XOR; in InstructionOpcodeToISD()
1793 case Load: return ISD::LOAD; in InstructionOpcodeToISD()
1794 case Store: return ISD::STORE; in InstructionOpcodeToISD()
1799 case Trunc: return ISD::TRUNCATE; in InstructionOpcodeToISD()
1800 case ZExt: return ISD::ZERO_EXTEND; in InstructionOpcodeToISD()
1801 case SExt: return ISD::SIGN_EXTEND; in InstructionOpcodeToISD()
1802 case FPToUI: return ISD::FP_TO_UINT; in InstructionOpcodeToISD()
1803 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()
1804 case UIToFP: return ISD::UINT_TO_FP; in InstructionOpcodeToISD()
1805 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
1806 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
1807 case FPExt: return ISD::FP_EXTEND; in InstructionOpcodeToISD()
1808 case PtrToInt: return ISD::BITCAST; in InstructionOpcodeToISD()
1809 case IntToPtr: return ISD::BITCAST; in InstructionOpcodeToISD()
1810 case BitCast: return ISD::BITCAST; in InstructionOpcodeToISD()
1811 case AddrSpaceCast: return ISD::ADDRSPACECAST; in InstructionOpcodeToISD()
1812 case ICmp: return ISD::SETCC; in InstructionOpcodeToISD()
1813 case FCmp: return ISD::SETCC; in InstructionOpcodeToISD()
1816 case Select: return ISD::SELECT; in InstructionOpcodeToISD()
1820 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; in InstructionOpcodeToISD()
1821 case InsertElement: return ISD::INSERT_VECTOR_ELT; in InstructionOpcodeToISD()
1822 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
1823 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1824 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1826 case Freeze: return ISD::FREEZE; in InstructionOpcodeToISD()
2210 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote && in isLoadBitCastBeneficial()
2211 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()) in isLoadBitCastBeneficial()