Lines Matching refs:ISD
142 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
175 SDValue Chain, ISD::ArgFlagsTy Flags,
187 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
203 const SmallVectorImpl<ISD::OutputArg> &Outs,
213 // Analyze return values of ISD::RET
237 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val);
240 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val);
243 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val);
344 /// LowerCallResult - Lower the result values of an ISD::CALL into the
348 /// ISD::CALL.
351 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
407 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
409 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
470 ISD::ArgFlagsTy Flags = Outs[i].Flags;
486 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
489 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
492 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
500 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
533 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
628 SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM,
644 if (Op->getOpcode() != ISD::ADD)
650 AM = ISD::POST_INC;
670 if ((Op.getOpcode() != ISD::INLINEASM &&
671 Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
709 // Need to transform ISD::PREFETCH into something that doesn't inherit
710 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
723 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
735 // Custom-handle ISD::READSTEADYCOUNTER because the target-independent SDNode
794 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
843 ISD::ArgFlagsTy Flags = Ins[i].Flags;
870 SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
873 ISD::SETNE);
996 DAG.getNode(ISD::ADD, DL, PtrVT,
1009 FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
1018 FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
1026 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1051 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1074 case ISD::TRUNCATE: {
1077 if (Op.getOpcode() != ISD::AssertSext)
1087 case ISD::LOAD:
1202 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1356 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1366 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1388 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1410 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1511 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1512 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
1513 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1514 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1515 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1516 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1517 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1518 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1519 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
1520 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1521 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1522 setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Custom);
1523 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1524 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1525 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1526 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1527 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1530 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1531 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1532 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1535 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1536 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1537 setOperationAction(ISD::SETCC, MVT::v4i8, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1541 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1542 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1543 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1545 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
1547 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1549 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1550 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1551 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1557 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1560 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) {
1568 setOperationAction(ISD::UADDO, VT, Custom);
1569 setOperationAction(ISD::USUBO, VT, Custom);
1570 setOperationAction(ISD::SADDO, VT, Expand);
1571 setOperationAction(ISD::SSUBO, VT, Expand);
1572 setOperationAction(ISD::UADDO_CARRY, VT, Expand);
1573 setOperationAction(ISD::USUBO_CARRY, VT, Expand);
1575 setOperationAction(ISD::UADDO_CARRY, MVT::i64, Custom);
1576 setOperationAction(ISD::USUBO_CARRY, MVT::i64, Custom);
1578 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1579 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1580 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1581 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1584 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1585 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1586 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1587 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1589 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1590 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
1591 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
1592 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
1594 setOperationAction(ISD::FSHL, MVT::i32, Legal);
1595 setOperationAction(ISD::FSHL, MVT::i64, Legal);
1596 setOperationAction(ISD::FSHR, MVT::i32, Legal);
1597 setOperationAction(ISD::FSHR, MVT::i64, Legal);
1600 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1601 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1602 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1603 ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
1609 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1610 ISD::FPOW, ISD::FCOPYSIGN}) {
1617 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1618 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1619 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1625 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1629 setOperationAction(ISD::BR_CC, VT, Expand);
1630 setOperationAction(ISD::SELECT_CC, VT, Expand);
1633 setOperationAction(ISD::BR_CC, VT, Expand);
1634 setOperationAction(ISD::SELECT_CC, VT, Expand);
1636 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1646 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1647 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
1648 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1650 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1651 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE,
1653 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1654 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1655 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1656 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1657 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1658 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, ISD::FLDEXP,
1660 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
1662 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1663 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1664 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1665 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE,
1666 ISD::SPLAT_VECTOR,
1677 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1678 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1679 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1686 setOperationAction(ISD::SELECT, VT, Promote);
1687 AddPromotedToType(ISD::SELECT, VT, VT32);
1689 setOperationAction(ISD::SRA, VT, Custom);
1690 setOperationAction(ISD::SHL, VT, Custom);
1691 setOperationAction(ISD::SRL, VT, Custom);
1696 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1697 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1698 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1699 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1700 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1701 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1703 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1704 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1705 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1710 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
1712 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
1713 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
1714 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
1715 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
1717 setOperationAction(ISD::ADD, NativeVT, Legal);
1718 setOperationAction(ISD::SUB, NativeVT, Legal);
1719 setOperationAction(ISD::MUL, NativeVT, Legal);
1720 setOperationAction(ISD::AND, NativeVT, Legal);
1721 setOperationAction(ISD::OR, NativeVT, Legal);
1722 setOperationAction(ISD::XOR, NativeVT, Legal);
1725 setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal);
1726 setOperationAction(ISD::BSWAP, NativeVT, Legal);
1727 setOperationAction(ISD::BITREVERSE, NativeVT, Legal);
1732 setOperationAction(ISD::SMIN, VT, Legal);
1733 setOperationAction(ISD::SMAX, VT, Legal);
1734 setOperationAction(ISD::UMIN, VT, Legal);
1735 setOperationAction(ISD::UMAX, VT, Legal);
1744 setOperationAction(ISD::LOAD, VT, Custom);
1745 setOperationAction(ISD::STORE, VT, Custom);
1750 setOperationAction(ISD::LOAD, VT, Custom);
1751 setOperationAction(ISD::STORE, VT, Custom);
1757 setCondCodeAction(ISD::SETNE, VT, Expand);
1758 setCondCodeAction(ISD::SETLE, VT, Expand);
1759 setCondCodeAction(ISD::SETGE, VT, Expand);
1760 setCondCodeAction(ISD::SETLT, VT, Expand);
1761 setCondCodeAction(ISD::SETULE, VT, Expand);
1762 setCondCodeAction(ISD::SETUGE, VT, Expand);
1763 setCondCodeAction(ISD::SETULT, VT, Expand);
1768 setCondCodeAction(ISD::SETGE, VT, Expand);
1769 setCondCodeAction(ISD::SETGT, VT, Expand);
1770 setCondCodeAction(ISD::SETUGE, VT, Expand);
1771 setCondCodeAction(ISD::SETUGT, VT, Expand);
1775 setOperationAction(ISD::BITCAST, MVT::i8, Custom);
1776 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1777 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
1778 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1781 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1784 setOperationAction(ISD::FMA, MVT::f64, Expand);
1785 setOperationAction(ISD::FADD, MVT::f64, Expand);
1786 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1787 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1788 setOperationAction(ISD::FDIV, MVT::f32, Custom);
1790 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1791 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1793 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1794 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1795 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1796 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1797 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1798 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1799 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1800 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1801 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1802 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1803 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1804 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1808 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1809 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1810 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1811 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1813 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
1814 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
1822 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
1823 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
1829 setOperationAction(ISD::ROTL, MVT::i32, Legal);
1830 setOperationAction(ISD::ROTL, MVT::i64, Legal);
1831 setOperationAction(ISD::ROTR, MVT::i32, Legal);
1832 setOperationAction(ISD::ROTR, MVT::i64, Legal);
1835 setOperationAction(ISD::FADD, MVT::f64, Legal);
1836 setOperationAction(ISD::FSUB, MVT::f64, Legal);
1839 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1840 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1841 setOperationAction(ISD::FMUL, MVT::f64, Legal);
1844 setTargetDAGCombine(ISD::OR);
1845 setTargetDAGCombine(ISD::TRUNCATE);
1846 setTargetDAGCombine(ISD::VSELECT);
2011 SDValue Trap = DAG.getNode(ISD::TRAP, dl, MVT::Other, Chain);
2012 if (LS->getOpcode() == ISD::LOAD)
2107 Info.opc = ISD::INTRINSIC_W_CHAIN;
2137 Info.opc = ISD::INTRINSIC_W_CHAIN;
2171 return isOperationLegalOrCustom(ISD::FMA, VT);
2195 return Op.getOpcode() == ISD::CONCAT_VECTORS ||
2242 if (Addr.getOpcode() == ISD::ADD) {
2322 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2349 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2380 case ISD::BUILD_VECTOR:
2384 case ISD::SPLAT_VECTOR:
2396 case ISD::SHL:
2399 case ISD::SRA:
2402 case ISD::SRL:
2457 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy,
2582 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2595 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2596 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2597 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2598 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2645 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2711 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2748 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2762 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2765 SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2811 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2816 return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2830 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, Width);
2850 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, Width);
2864 SDValue X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i16, P);
2889 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG));
2918 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats);
2930 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Lo, Hi);
2938 DAG.getNode(ISD::BUILD_PAIR, dl, PairTy,
2988 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
3107 ISD::LoadExtType ET = LN->getExtensionType();
3112 LN->getAddressingMode(), ISD::ZEXTLOAD, MVT::i32, dl, LN->getChain(),
3128 if (ET == ISD::SEXTLOAD) {
3130 } else if (ET != ISD::NON_EXTLOAD) {
3224 BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
3251 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3277 if (Opc == ISD::UADDO) {
3278 SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
3280 ISD::SETEQ);
3283 if (Opc == ISD::USUBO) {
3284 SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
3286 DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
3300 if (Opc == ISD::UADDO_CARRY)
3328 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
3344 if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
3362 case ISD::FDIV:
3364 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3365 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
3366 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
3367 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
3368 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3369 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3370 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3371 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
3372 case ISD::LOAD: return LowerLoad(Op, DAG);
3373 case ISD::STORE: return LowerStore(Op, DAG);
3374 case ISD::UADDO:
3375 case ISD::USUBO: return LowerUAddSubO(Op, DAG);
3376 case ISD::UADDO_CARRY:
3377 case ISD::USUBO_CARRY: return LowerUAddSubOCarry(Op, DAG);
3378 case ISD::SRA:
3379 case ISD::SHL:
3380 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
3381 case ISD::ROTL: return LowerROTL(Op, DAG);
3382 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3383 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3384 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
3385 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3386 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3387 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3388 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
3389 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
3390 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3391 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3392 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3393 case ISD::VASTART: return LowerVASTART(Op, DAG);
3394 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3395 case ISD::SETCC: return LowerSETCC(Op, DAG);
3396 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
3397 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3398 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
3399 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
3400 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
3401 case ISD::READSTEADYCOUNTER: return LowerREADSTEADYCOUNTER(Op, DAG);
3426 case ISD::STORE:
3451 case ISD::SRL:
3452 case ISD::SRA:
3453 case ISD::SHL:
3455 case ISD::BITCAST:
3482 if (Opc == ISD::TRUNCATE) {
3485 if (Op0.getOpcode() == ISD::BUILD_PAIR) {
3493 return DCI.DAG.getNode(ISD::TRUNCATE, dl, TruncTy, Elem0);
3510 } else if (Opc == ISD::VSELECT) {
3515 if (Cond->getOpcode() == ISD::XOR) {
3518 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
3523 } else if (Opc == ISD::TRUNCATE) {
3526 if (Op0.getOpcode() == ISD::BUILD_PAIR) {
3534 return DCI.DAG.getNode(ISD::TRUNCATE, dl, TruncTy, Elem0);
3536 } else if (Opc == ISD::OR) {
3544 if (Shl.getOpcode() != ISD::SHL)
3547 if (Shl.getOpcode() != ISD::SHL || Zxt.getOpcode() != ISD::ZERO_EXTEND)
3555 SDValue T0 = DCI.DAG.getNode(ISD::SHL, dl, ty(S), S,
3729 const SmallVectorImpl<ISD::OutputArg> &Outs,
3731 const SmallVectorImpl<ISD::InputArg> &Ins,
3840 ISD::LoadExtType ExtTy, EVT NewVT) const {