Lines Matching refs:ISD
46 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
59 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Split_64()
85 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Ret_Split_64()
109 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in Analyze_CC_Sparc64_Full()
159 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in Analyze_CC_Sparc64_Half()
196 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
203 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
210 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in RetCC_Sparc64_Full()
217 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in RetCC_Sparc64_Half()
237 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn()
247 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
258 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
292 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
295 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
343 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
373 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
376 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
379 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
388 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
394 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
395 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
419 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
433 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments_32()
491 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
492 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
500 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
502 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
504 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
547 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
548 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
579 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerFormalArguments_32()
618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerFormalArguments_32()
628 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments_64()
653 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
660 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
664 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
673 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
728 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); in LowerFormalArguments_64()
825 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall_32()
827 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall_32()
855 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall_32()
899 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; in LowerCall_32()
914 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
917 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
920 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
923 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
936 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
956 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
969 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
972 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
975 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
990 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
999 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
1004 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
1018 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
1029 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
1037 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32()
1116 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32); in LowerCall_32()
1121 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, in LowerCall_32()
1127 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi, in LowerCall_32()
1180 ArrayRef<ISD::OutputArg> Outs) { in fixupVariableFloatArgs()
1282 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1285 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1288 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1295 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1307 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff); in LowerCall_64()
1309 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff); in LowerCall_64()
1335 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, in LowerCall_64()
1342 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
1344 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); in LowerCall_64()
1366 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff); in LowerCall_64()
1373 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall_64()
1463 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
1475 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1482 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1486 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1495 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()
1517 static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) { in intCondCCodeToRcond()
1521 case ISD::SETEQ: in intCondCCodeToRcond()
1523 case ISD::SETNE: in intCondCCodeToRcond()
1525 case ISD::SETLT: in intCondCCodeToRcond()
1527 case ISD::SETGT: in intCondCCodeToRcond()
1529 case ISD::SETLE: in intCondCCodeToRcond()
1531 case ISD::SETGE: in intCondCCodeToRcond()
1538 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { in IntCondCCodeToICC()
1541 case ISD::SETEQ: return SPCC::ICC_E; in IntCondCCodeToICC()
1542 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1543 case ISD::SETLT: return SPCC::ICC_L; in IntCondCCodeToICC()
1544 case ISD::SETGT: return SPCC::ICC_G; in IntCondCCodeToICC()
1545 case ISD::SETLE: return SPCC::ICC_LE; in IntCondCCodeToICC()
1546 case ISD::SETGE: return SPCC::ICC_GE; in IntCondCCodeToICC()
1547 case ISD::SETULT: return SPCC::ICC_CS; in IntCondCCodeToICC()
1548 case ISD::SETULE: return SPCC::ICC_LEU; in IntCondCCodeToICC()
1549 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
1550 case ISD::SETUGE: return SPCC::ICC_CC; in IntCondCCodeToICC()
1556 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC()
1559 case ISD::SETEQ: in FPCondCCodeToFCC()
1560 case ISD::SETOEQ: return SPCC::FCC_E; in FPCondCCodeToFCC()
1561 case ISD::SETNE: in FPCondCCodeToFCC()
1562 case ISD::SETUNE: return SPCC::FCC_NE; in FPCondCCodeToFCC()
1563 case ISD::SETLT: in FPCondCCodeToFCC()
1564 case ISD::SETOLT: return SPCC::FCC_L; in FPCondCCodeToFCC()
1565 case ISD::SETGT: in FPCondCCodeToFCC()
1566 case ISD::SETOGT: return SPCC::FCC_G; in FPCondCCodeToFCC()
1567 case ISD::SETLE: in FPCondCCodeToFCC()
1568 case ISD::SETOLE: return SPCC::FCC_LE; in FPCondCCodeToFCC()
1569 case ISD::SETGE: in FPCondCCodeToFCC()
1570 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
1571 case ISD::SETULT: return SPCC::FCC_UL; in FPCondCCodeToFCC()
1572 case ISD::SETULE: return SPCC::FCC_ULE; in FPCondCCodeToFCC()
1573 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
1574 case ISD::SETUGE: return SPCC::FCC_UGE; in FPCondCCodeToFCC()
1575 case ISD::SETUO: return SPCC::FCC_U; in FPCondCCodeToFCC()
1576 case ISD::SETO: return SPCC::FCC_O; in FPCondCCodeToFCC()
1577 case ISD::SETONE: return SPCC::FCC_LG; in FPCondCCodeToFCC()
1578 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
1611 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { in SparcTargetLowering()
1616 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1617 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1618 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1620 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1621 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1622 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1628 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1629 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
1630 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
1631 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal); in SparcTargetLowering()
1634 setOperationAction(ISD::LOAD, MVT::i64, Custom); in SparcTargetLowering()
1635 setOperationAction(ISD::STORE, MVT::i64, Custom); in SparcTargetLowering()
1644 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in SparcTargetLowering()
1645 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1646 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
1651 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SparcTargetLowering()
1662 setOperationAction(ISD::GlobalAddress, PtrVT, Custom); in SparcTargetLowering()
1663 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom); in SparcTargetLowering()
1664 setOperationAction(ISD::ConstantPool, PtrVT, Custom); in SparcTargetLowering()
1665 setOperationAction(ISD::BlockAddress, PtrVT, Custom); in SparcTargetLowering()
1668 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1669 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1670 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
1673 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1674 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1675 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1676 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1680 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
1681 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
1682 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1683 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1687 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1688 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1689 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
1690 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1693 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1694 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1695 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
1696 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1699 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in SparcTargetLowering()
1700 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in SparcTargetLowering()
1701 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in SparcTargetLowering()
1702 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in SparcTargetLowering()
1703 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); in SparcTargetLowering()
1704 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand); in SparcTargetLowering()
1706 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1707 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1710 setOperationAction(ISD::SELECT, MVT::i32, Expand); in SparcTargetLowering()
1711 setOperationAction(ISD::SELECT, MVT::f32, Expand); in SparcTargetLowering()
1712 setOperationAction(ISD::SELECT, MVT::f64, Expand); in SparcTargetLowering()
1713 setOperationAction(ISD::SELECT, MVT::f128, Expand); in SparcTargetLowering()
1715 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1716 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1717 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1718 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1721 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
1722 setOperationAction(ISD::BRIND, MVT::Other, Expand); in SparcTargetLowering()
1723 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in SparcTargetLowering()
1724 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1725 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1726 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1727 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1729 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1730 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1731 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1732 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1734 setOperationAction(ISD::ADDC, MVT::i32, Custom); in SparcTargetLowering()
1735 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1736 setOperationAction(ISD::SUBC, MVT::i32, Custom); in SparcTargetLowering()
1737 setOperationAction(ISD::SUBE, MVT::i32, Custom); in SparcTargetLowering()
1740 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
1741 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
1742 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
1743 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
1744 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
1745 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering()
1746 setOperationAction(ISD::SELECT, MVT::i64, Expand); in SparcTargetLowering()
1747 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
1748 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
1749 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1751 setOperationAction(ISD::CTPOP, MVT::i64, in SparcTargetLowering()
1753 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1754 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1755 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in SparcTargetLowering()
1756 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1757 setOperationAction(ISD::ROTR , MVT::i64, Expand); in SparcTargetLowering()
1758 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in SparcTargetLowering()
1779 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1781 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1784 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in SparcTargetLowering()
1785 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in SparcTargetLowering()
1788 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1789 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1790 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); in SparcTargetLowering()
1791 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); in SparcTargetLowering()
1796 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1797 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1800 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1801 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1802 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1803 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1804 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1805 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1806 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1807 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1808 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1809 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1810 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1811 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
1812 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
1813 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
1814 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
1815 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
1816 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
1817 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
1818 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
1819 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in SparcTargetLowering()
1820 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1821 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1822 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
1823 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1824 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1825 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
1827 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1828 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1829 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1832 setOperationAction(ISD::MULHU, MVT::i32, Expand); in SparcTargetLowering()
1833 setOperationAction(ISD::MULHS, MVT::i32, Expand); in SparcTargetLowering()
1834 setOperationAction(ISD::MUL, MVT::i32, Expand); in SparcTargetLowering()
1838 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1839 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1842 setOperationAction(ISD::SDIV, MVT::i32, Expand); in SparcTargetLowering()
1845 setOperationAction(ISD::UDIV, MVT::i32, Expand); in SparcTargetLowering()
1853 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1854 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1855 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
1856 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
1858 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
1859 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
1861 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1862 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1863 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1867 setOperationAction(ISD::VASTART , MVT::Other, Custom); in SparcTargetLowering()
1869 setOperationAction(ISD::VAARG , MVT::Other, Custom); in SparcTargetLowering()
1871 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
1872 setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal); in SparcTargetLowering()
1875 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in SparcTargetLowering()
1876 setOperationAction(ISD::VAEND , MVT::Other, Expand); in SparcTargetLowering()
1877 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in SparcTargetLowering()
1878 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); in SparcTargetLowering()
1879 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in SparcTargetLowering()
1883 setOperationAction(ISD::CTPOP, MVT::i32, in SparcTargetLowering()
1887 setOperationAction(ISD::LOAD, MVT::f128, Legal); in SparcTargetLowering()
1888 setOperationAction(ISD::STORE, MVT::f128, Legal); in SparcTargetLowering()
1890 setOperationAction(ISD::LOAD, MVT::f128, Custom); in SparcTargetLowering()
1891 setOperationAction(ISD::STORE, MVT::f128, Custom); in SparcTargetLowering()
1895 setOperationAction(ISD::FADD, MVT::f128, Legal); in SparcTargetLowering()
1896 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1897 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1898 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1899 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1900 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1901 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1903 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1904 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1906 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1907 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1920 setOperationAction(ISD::FADD, MVT::f128, Custom); in SparcTargetLowering()
1921 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
1922 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1923 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1924 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1925 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1926 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1928 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
1929 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1930 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
1975 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
1976 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
1980 setOperationAction(ISD::FMUL, MVT::f32, Promote); in SparcTargetLowering()
1985 setTargetDAGCombine(ISD::BITCAST); in SparcTargetLowering()
1988 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in SparcTargetLowering()
1990 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in SparcTargetLowering()
2078 ISD::CondCode CC, unsigned &SPCC) { in LookThroughSetCC()
2079 if (isNullConstant(RHS) && CC == ISD::SETNE && in LookThroughSetCC()
2129 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeHiLoPair()
2155 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx); in makeAddress()
2176 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); in makeAddress()
2179 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); in makeAddress()
2185 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); in makeAddress()
2188 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeAddress()
2272 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
2291 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); in LowerGlobalTLSAddress()
2306 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
2308 return DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalTLSAddress()
2442 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2475 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2482 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2550 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in LowerFP_TO_SINT()
2576 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); in LowerSINT_TO_FP()
2625 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
2643 isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC)) in LowerBR_CC()
2677 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
2701 isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC) && IsEligibleType) in LowerSELECT_CC()
2739 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT), in LowerVASTART()
2757 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, in LowerVAARG()
2816 Size = DAG.getNode(ISD::ADD, dl, VT, Size, in LowerDYNAMIC_STACKALLOC()
2823 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
2828 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, in LowerDYNAMIC_STACKALLOC()
2864 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2869 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2910 SDValue Ptr = DAG.getNode(ISD::ADD, in LowerRETURNADDR()
2922 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2965 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Load()
2989 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Load()
3033 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Store()
3039 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Store()
3054 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue()); in LowerSTORE()
3066 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3115 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
3116 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
3118 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
3121 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
3122 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
3124 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
3131 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3132 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3133 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3134 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3147 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
3148 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
3149 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, in LowerADDC_ADDE_SUBC_SUBE()
3152 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); in LowerADDC_ADDE_SUBC_SUBE()
3163 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3165 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
3179 HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO()
3180 HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
3196 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO()
3197 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
3200 ISD::SETNE); in LowerUMULO_SMULO()
3245 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this, in LowerOperation()
3247 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG, in LowerOperation()
3249 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
3250 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
3251 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
3252 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
3253 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3255 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3257 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, in LowerOperation()
3259 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3261 case ISD::BR_CC: in LowerOperation()
3263 case ISD::SELECT_CC: in LowerOperation()
3265 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); in LowerOperation()
3266 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
3267 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, in LowerOperation()
3270 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
3271 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
3272 case ISD::FADD: return LowerF128Op(Op, DAG, in LowerOperation()
3274 case ISD::FSUB: return LowerF128Op(Op, DAG, in LowerOperation()
3276 case ISD::FMUL: return LowerF128Op(Op, DAG, in LowerOperation()
3278 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
3280 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
3282 case ISD::FABS: in LowerOperation()
3283 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
3284 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
3285 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
3286 case ISD::ADDC: in LowerOperation()
3287 case ISD::ADDE: in LowerOperation()
3288 case ISD::SUBC: in LowerOperation()
3289 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
3290 case ISD::UMULO: in LowerOperation()
3291 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
3292 case ISD::ATOMIC_LOAD: in LowerOperation()
3293 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG); in LowerOperation()
3294 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
3326 case ISD::BITCAST: in PerformDAGCombine()
3604 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3605 case ISD::FP_TO_UINT: in ReplaceNodeResults()
3610 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
3619 case ISD::READCYCLECOUNTER: { in ReplaceNodeResults()
3624 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops); in ReplaceNodeResults()
3629 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3630 case ISD::UINT_TO_FP: in ReplaceNodeResults()
3636 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
3645 case ISD::LOAD: { in ReplaceNodeResults()
3659 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes); in ReplaceNodeResults()