Lines Matching refs:ISD
61 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
62 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
66 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
67 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
68 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
75 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
76 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
77 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
78 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
79 setOperationAction(ISD::SHL, MVT::i16, Custom); in MSP430TargetLowering()
80 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
81 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
82 setOperationAction(ISD::ROTR, MVT::i8, Expand); in MSP430TargetLowering()
83 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
84 setOperationAction(ISD::ROTR, MVT::i16, Expand); in MSP430TargetLowering()
85 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in MSP430TargetLowering()
86 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); in MSP430TargetLowering()
87 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); in MSP430TargetLowering()
88 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in MSP430TargetLowering()
89 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in MSP430TargetLowering()
90 setOperationAction(ISD::BR_CC, MVT::i16, Custom); in MSP430TargetLowering()
91 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in MSP430TargetLowering()
92 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
93 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
94 setOperationAction(ISD::SELECT, MVT::i8, Expand); in MSP430TargetLowering()
95 setOperationAction(ISD::SELECT, MVT::i16, Expand); in MSP430TargetLowering()
96 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
98 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering()
99 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); in MSP430TargetLowering()
100 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); in MSP430TargetLowering()
101 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in MSP430TargetLowering()
102 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in MSP430TargetLowering()
104 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
105 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
106 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
107 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
108 setOperationAction(ISD::CTPOP, MVT::i8, Expand); in MSP430TargetLowering()
109 setOperationAction(ISD::CTPOP, MVT::i16, Expand); in MSP430TargetLowering()
111 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); in MSP430TargetLowering()
112 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); in MSP430TargetLowering()
113 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); in MSP430TargetLowering()
114 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); in MSP430TargetLowering()
115 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); in MSP430TargetLowering()
116 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); in MSP430TargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MSP430TargetLowering()
121 setOperationAction(ISD::MUL, MVT::i8, Promote); in MSP430TargetLowering()
122 setOperationAction(ISD::MULHS, MVT::i8, Promote); in MSP430TargetLowering()
123 setOperationAction(ISD::MULHU, MVT::i8, Promote); in MSP430TargetLowering()
124 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Promote); in MSP430TargetLowering()
125 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Promote); in MSP430TargetLowering()
126 setOperationAction(ISD::MUL, MVT::i16, LibCall); in MSP430TargetLowering()
127 setOperationAction(ISD::MULHS, MVT::i16, Expand); in MSP430TargetLowering()
128 setOperationAction(ISD::MULHU, MVT::i16, Expand); in MSP430TargetLowering()
129 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); in MSP430TargetLowering()
130 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); in MSP430TargetLowering()
132 setOperationAction(ISD::UDIV, MVT::i8, Promote); in MSP430TargetLowering()
133 setOperationAction(ISD::UDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
134 setOperationAction(ISD::UREM, MVT::i8, Promote); in MSP430TargetLowering()
135 setOperationAction(ISD::SDIV, MVT::i8, Promote); in MSP430TargetLowering()
136 setOperationAction(ISD::SDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
137 setOperationAction(ISD::SREM, MVT::i8, Promote); in MSP430TargetLowering()
138 setOperationAction(ISD::UDIV, MVT::i16, LibCall); in MSP430TargetLowering()
139 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
140 setOperationAction(ISD::UREM, MVT::i16, LibCall); in MSP430TargetLowering()
141 setOperationAction(ISD::SDIV, MVT::i16, LibCall); in MSP430TargetLowering()
142 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
143 setOperationAction(ISD::SREM, MVT::i16, LibCall); in MSP430TargetLowering()
146 setOperationAction(ISD::VASTART, MVT::Other, Custom); in MSP430TargetLowering()
147 setOperationAction(ISD::VAARG, MVT::Other, Expand); in MSP430TargetLowering()
148 setOperationAction(ISD::VAEND, MVT::Other, Expand); in MSP430TargetLowering()
149 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in MSP430TargetLowering()
150 setOperationAction(ISD::JumpTable, MVT::i16, Custom); in MSP430TargetLowering()
156 const ISD::CondCode Cond; in MSP430TargetLowering()
159 { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID }, in MSP430TargetLowering()
160 { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID }, in MSP430TargetLowering()
163 { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
164 { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
167 { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID }, in MSP430TargetLowering()
168 { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID }, in MSP430TargetLowering()
171 { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
172 { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
175 { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID }, in MSP430TargetLowering()
176 { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID }, in MSP430TargetLowering()
179 { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID }, in MSP430TargetLowering()
181 { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID }, in MSP430TargetLowering()
184 { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID }, in MSP430TargetLowering()
186 { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID }, in MSP430TargetLowering()
189 { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID }, in MSP430TargetLowering()
191 { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID }, in MSP430TargetLowering()
194 { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID }, in MSP430TargetLowering()
196 { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID }, in MSP430TargetLowering()
199 { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ }, in MSP430TargetLowering()
200 { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE }, in MSP430TargetLowering()
201 { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE }, in MSP430TargetLowering()
202 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, in MSP430TargetLowering()
203 { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE }, in MSP430TargetLowering()
204 { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT }, in MSP430TargetLowering()
205 { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ }, in MSP430TargetLowering()
206 { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE }, in MSP430TargetLowering()
207 { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE }, in MSP430TargetLowering()
208 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, in MSP430TargetLowering()
209 { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE }, in MSP430TargetLowering()
210 { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT }, in MSP430TargetLowering()
213 { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID }, in MSP430TargetLowering()
214 { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID }, in MSP430TargetLowering()
215 { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID }, in MSP430TargetLowering()
216 { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID }, in MSP430TargetLowering()
217 { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID }, in MSP430TargetLowering()
218 { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID }, in MSP430TargetLowering()
219 { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID }, in MSP430TargetLowering()
220 { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID }, in MSP430TargetLowering()
226 { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID }, in MSP430TargetLowering()
227 { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
228 { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
229 { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID }, in MSP430TargetLowering()
230 { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID }, in MSP430TargetLowering()
231 { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID }, in MSP430TargetLowering()
232 { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID }, in MSP430TargetLowering()
233 { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
234 { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID }, in MSP430TargetLowering()
235 { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID }, in MSP430TargetLowering()
236 { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID }, in MSP430TargetLowering()
237 { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID }, in MSP430TargetLowering()
241 { RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID }, in MSP430TargetLowering()
242 { RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID }, in MSP430TargetLowering()
243 { RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID }, in MSP430TargetLowering()
250 if (LC.Cond != ISD::SETCC_INVALID) in MSP430TargetLowering()
342 case ISD::SHL: // FALLTHROUGH in LowerOperation()
343 case ISD::SRL: in LowerOperation()
344 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
345 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
346 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
347 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); in LowerOperation()
348 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
349 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
350 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
351 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation()
352 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); in LowerOperation()
353 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); in LowerOperation()
354 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
355 case ISD::JumpTable: return LowerJumpTable(Op, DAG); in LowerOperation()
442 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeVarArgs()
447 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeVarArgs()
500 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags; in AnalyzeArguments()
551 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeRetResult()
556 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeRetResult()
569 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments()
590 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
592 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
620 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCArguments()
662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
669 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
678 ISD::ArgFlagsTy Flags = Ins[i].Flags; in LowerCCCArguments()
716 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerCCCArguments()
727 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
737 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
807 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo()
809 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCCallTo()
838 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
841 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
844 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
859 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, in LowerCCCCallTo()
863 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCCCCallTo()
884 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCCCCallTo()
937 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
979 case ISD::SHL: in LowerShifts()
982 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim); in LowerShifts()
984 case ISD::SRA: in LowerShifts()
985 case ISD::SRL: in LowerShifts()
987 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim); in LowerShifts()
988 Victim = (Opc == ISD::SRA) in LowerShifts()
989 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim, in LowerShifts()
997 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
1005 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), in LowerShifts()
1043 ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) { in EmitCMP()
1051 case ISD::SETEQ: in EmitCMP()
1055 if (LHS.getOpcode() == ISD::Constant) in EmitCMP()
1058 case ISD::SETNE: in EmitCMP()
1062 if (LHS.getOpcode() == ISD::Constant) in EmitCMP()
1065 case ISD::SETULE: in EmitCMP()
1068 case ISD::SETUGE: in EmitCMP()
1079 case ISD::SETUGT: in EmitCMP()
1082 case ISD::SETULT: in EmitCMP()
1093 case ISD::SETLE: in EmitCMP()
1096 case ISD::SETGE: in EmitCMP()
1107 case ISD::SETGT: in EmitCMP()
1110 case ISD::SETLT: in EmitCMP()
1130 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
1154 (LHS.getOpcode() == ISD::AND || in LowerSETCC()
1155 (LHS.getOpcode() == ISD::TRUNCATE && in LowerSETCC()
1156 LHS.getOperand(0).getOpcode() == ISD::AND)); in LowerSETCC()
1157 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
1201 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
1202 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); in LowerSETCC()
1204 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); in LowerSETCC()
1219 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
1238 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, in LowerSIGN_EXTEND()
1239 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), in LowerSIGN_EXTEND()
1278 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset), in LowerRETURNADDR()
1336 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
1340 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPostIndexedAddressParts()
1347 if (Op->getOpcode() != ISD::ADD) in getPostIndexedAddressParts()
1358 AM = ISD::POST_INC; in getPostIndexedAddressParts()