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Searched refs:GENMASK (Results 1 – 25 of 159) sorted by relevance

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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac3_mac.h24 #define MT_RXD0_LENGTH GENMASK(15, 0)
25 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
30 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
39 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
45 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
50 #define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27)
56 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
57 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
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H A Dmt76_connac2_mac.h35 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
36 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
37 #define MT_TX_FREE_COUNT GENMASK(12, 0)
39 #define MT_TX_FREE_STATUS GENMASK(14, 13)
40 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
43 #define MT_TX_FREE_RATE GENMASK(13, 0)
45 #define MT_TXD0_Q_IDX GENMASK(31, 25)
46 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
47 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
48 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
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H A Dmt76x02_regs.h19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
20 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
22 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
54 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
55 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
56 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
68 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
71 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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H A Dmt792x_regs.h37 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
38 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
41 #define MT_IFS_EIFS GENMASK(8, 0)
42 #define MT_IFS_RIFS GENMASK(14, 10)
43 #define MT_IFS_SIFS GENMASK(22, 16)
44 #define MT_IFS_SLOT GENMASK(30, 24)
47 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
58 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
66 #define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30)
67 #define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
33 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
57 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
58 #define MT_RXD2_NORMAL_TID GENMASK(11, 8)
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H A Dregs.h14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
47 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
56 #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
24 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
29 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
30 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
31 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
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H A Dregs.h43 #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
48 #define MT7663_TOP_MISC2_FW_STATE GENMASK(3, 1)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
56 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
60 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
61 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
84 #define MT7663_MCU_PCIE_REMAP_2_OFFSET GENMASK(15, 0)
85 #define MT7663_MCU_PCIE_REMAP_2_BASE GENMASK(31, 16)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
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/freebsd/sys/contrib/dev/rtw89/
H A Dreg.h12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
54 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
56 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
57 #define B_AX_EF_PGTS_MASK GENMASK(23, 20)
60 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
63 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
66 #define B_AX_EF_ADDR_MASK GENMASK(26, 16)
67 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
72 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
92 #define B_AX_BTMODE_MASK GENMASK(
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H A Dtxrx.h10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
17 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
18 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
19 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
20 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
63 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(3
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H A Dfw.h25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(1
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H A Dcam.h12 #define RTW89_BSSID_MATCH_ALL GENMASK(5, 0)
13 #define RTW89_BSSID_MATCH_5_BYTES GENMASK(4, 0)
17 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)); in FWCMD_SET_ADDR_IDX()
22 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8)); in FWCMD_SET_ADDR_OFFSET()
27 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16)); in FWCMD_SET_ADDR_LEN()
37 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1)); in FWCMD_SET_ADDR_NET_TYPE()
42 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3)); in FWCMD_SET_ADDR_BCN_HIT_COND()
47 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5)); in FWCMD_SET_ADDR_HIT_RULE()
57 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8)); in FWCMD_SET_ADDR_ADDR_MASK()
62 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(1 in FWCMD_SET_ADDR_MASK_SEL()
[all...]
/freebsd/sys/contrib/dev/athk/ath12k/
H A Dhal_desc.h11 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
13 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
14 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8)
15 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12)
569 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
570 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
571 #define HAL_TLV_USR_ID GENMASK(31, 26)
580 #define HAL_TLV_64_HDR_TAG GENMASK(9, 1)
581 #define HAL_TLV_64_HDR_LEN GENMASK(21, 10)
588 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
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H A Dhal_rx.h29 le32_get_bits((__val), GENMASK(7, 0))
32 le32_get_bits((__val), GENMASK(15, 8))
35 le32_get_bits((__val), GENMASK(23, 16))
38 le32_get_bits((__val), GENMASK(31, 24))
234 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
242 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16)
244 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0)
248 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20)
250 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
251 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
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H A Dhal_tx.h69 #define HAL_TX_PHY_DESC_INFO0_BF_TYPE GENMASK(17, 16)
71 #define HAL_TX_PHY_DESC_INFO0_PKT_TYPE GENMASK(24, 21)
72 #define HAL_TX_PHY_DESC_INFO0_BANDWIDTH GENMASK(30, 28)
73 #define HAL_TX_PHY_DESC_INFO1_MCS GENMASK(3, 0)
75 #define HAL_TX_PHY_DESC_INFO2_NSS GENMASK(23, 21)
76 #define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW GENMASK(6, 4)
77 #define HAL_TX_PHY_DESC_INFO3_LTF_SIZE GENMASK(20, 19)
78 #define HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL GENMASK(17, 15)
87 #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0 GENMASK(15, 0)
88 #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16 GENMASK(31, 16)
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H A Drx_desc.h25 #define RX_MPDU_START_INFO0_REO_DEST_IND GENMASK(4, 0)
26 #define RX_MPDU_START_INFO0_LMAC_PEER_ID_MSB GENMASK(6, 5)
31 #define RX_MPDU_START_INFO0_RXDMA0_SRC_RING_SEL GENMASK(13, 11)
32 #define RX_MPDU_START_INFO0_RXDMA0_DST_RING_SEL GENMASK(16, 14)
39 #define RX_MPDU_START_INFO1_REO_QUEUE_DESC_HI GENMASK(7, 0)
40 #define RX_MPDU_START_INFO1_RECV_QUEUE_NUM GENMASK(23, 8)
46 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)
47 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
48 #define RX_MPDU_START_INFO2_MESH_STA GENMASK(9, 8)
50 #define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(14, 11)
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H A Ddp.h86 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
185 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
186 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18)
191 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
192 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
193 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
242 #define ATH12k_DP_CC_COOKIE_SPT GENMASK(8, 0)
243 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
245 #define DP_REO_QREF_NUM GENMASK(31, 16)
365 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
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/freebsd/sys/contrib/dev/athk/ath11k/
H A Dhal_desc.h10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
13 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
14 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
475 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
476 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
477 #define HAL_TLV_USR_ID GENMASK(31, 26)
486 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
487 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8)
500 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)
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H A Dhal_rx.h195 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
203 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16)
205 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0)
209 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20)
211 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
212 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
214 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
216 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
217 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
219 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
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H A Drx_desc.h28 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
29 #define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)
131 #define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE GENMASK(12, 10)
355 #define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER GENMASK(13, 10)
361 #define RX_MPDU_START_INFO1_MPDU_SEQ_NUM GENMASK(31, 20)
365 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)
366 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
369 #define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10)
370 #define RX_MPDU_START_INFO2_TID GENMASK(17, 14)
371 #define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15)
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822c.h143 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
145 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
147 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
149 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
151 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
155 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
157 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
159 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
161 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
163 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
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H A Dfw.h93 #define RTW_H2C_W0_CMDID GENMASK(7, 0)
96 #define RTW_H2C_DEFAULT_PORT_W0_PORTID GENMASK(15, 8)
97 #define RTW_H2C_DEFAULT_PORT_W0_MACID GENMASK(23, 16)
392 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
394 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
396 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) in rtw_h2c_pkt_set_header()
398 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) in rtw_h2c_pkt_set_header()
408 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
410 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
413 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(
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H A Drtw8723d.h14 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
18 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
22 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
24 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
26 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
28 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
30 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
32 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h177 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
184 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
185 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
186 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
190 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
191 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
192 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
201 #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
202 #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)
209 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
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H A Dmac.h9 #define MT_TX_FREE_VER GENMASK(18, 16)
10 #define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0)
12 #define MT_TX_FREE_COUNT GENMASK(12, 0)
13 #define MT_TX_FREE_COUNT_V3 GENMASK(27, 24)
14 #define MT_TX_FREE_STAT GENMASK(14, 13)
15 #define MT_TX_FREE_STAT_V3 GENMASK(29, 28)
18 #define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0)
22 #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)
23 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
24 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
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