16c92544dSBjoern A. Zeeb /* SPDX-License-Identifier: ISC */ 26c92544dSBjoern A. Zeeb /* Copyright (C) 2020 MediaTek Inc. */ 36c92544dSBjoern A. Zeeb 46c92544dSBjoern A. Zeeb #ifndef __MT7915_MAC_H 56c92544dSBjoern A. Zeeb #define __MT7915_MAC_H 66c92544dSBjoern A. Zeeb 76c92544dSBjoern A. Zeeb #include "../mt76_connac2_mac.h" 86c92544dSBjoern A. Zeeb 96c92544dSBjoern A. Zeeb #define MT_TX_FREE_VER GENMASK(18, 16) 106c92544dSBjoern A. Zeeb #define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0) 116c92544dSBjoern A. Zeeb /* 0: success, others: dropped */ 12*cbb3ec25SBjoern A. Zeeb #define MT_TX_FREE_COUNT GENMASK(12, 0) 13*cbb3ec25SBjoern A. Zeeb #define MT_TX_FREE_COUNT_V3 GENMASK(27, 24) 14*cbb3ec25SBjoern A. Zeeb #define MT_TX_FREE_STAT GENMASK(14, 13) 15*cbb3ec25SBjoern A. Zeeb #define MT_TX_FREE_STAT_V3 GENMASK(29, 28) 16*cbb3ec25SBjoern A. Zeeb #define MT_TX_FREE_MPDU_HEADER BIT(15) 17*cbb3ec25SBjoern A. Zeeb #define MT_TX_FREE_MPDU_HEADER_V3 BIT(30) 186c92544dSBjoern A. Zeeb #define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0) 196c92544dSBjoern A. Zeeb 206c92544dSBjoern A. Zeeb #define MT_TXS5_F0_FINAL_MPDU BIT(31) 216c92544dSBjoern A. Zeeb #define MT_TXS5_F0_QOS BIT(30) 226c92544dSBjoern A. Zeeb #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25) 236c92544dSBjoern A. Zeeb #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0) 246c92544dSBjoern A. Zeeb #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24) 256c92544dSBjoern A. Zeeb #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0) 266c92544dSBjoern A. Zeeb 276c92544dSBjoern A. Zeeb #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24) 286c92544dSBjoern A. Zeeb #define MT_TXS6_F0_NOISE_2 GENMASK(23, 16) 296c92544dSBjoern A. Zeeb #define MT_TXS6_F0_NOISE_1 GENMASK(15, 8) 306c92544dSBjoern A. Zeeb #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0) 316c92544dSBjoern A. Zeeb #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24) 326c92544dSBjoern A. Zeeb #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0) 336c92544dSBjoern A. Zeeb 346c92544dSBjoern A. Zeeb #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24) 356c92544dSBjoern A. Zeeb #define MT_TXS7_F0_RCPI_2 GENMASK(23, 16) 366c92544dSBjoern A. Zeeb #define MT_TXS7_F0_RCPI_1 GENMASK(15, 8) 376c92544dSBjoern A. Zeeb #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0) 386c92544dSBjoern A. Zeeb #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24) 396c92544dSBjoern A. Zeeb #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0) 406c92544dSBjoern A. Zeeb 416c92544dSBjoern A. Zeeb struct mt7915_dfs_pulse { 426c92544dSBjoern A. Zeeb u32 max_width; /* us */ 436c92544dSBjoern A. Zeeb int max_pwr; /* dbm */ 446c92544dSBjoern A. Zeeb int min_pwr; /* dbm */ 456c92544dSBjoern A. Zeeb u32 min_stgr_pri; /* us */ 466c92544dSBjoern A. Zeeb u32 max_stgr_pri; /* us */ 476c92544dSBjoern A. Zeeb u32 min_cr_pri; /* us */ 486c92544dSBjoern A. Zeeb u32 max_cr_pri; /* us */ 496c92544dSBjoern A. Zeeb }; 506c92544dSBjoern A. Zeeb 516c92544dSBjoern A. Zeeb struct mt7915_dfs_pattern { 526c92544dSBjoern A. Zeeb u8 enb; 536c92544dSBjoern A. Zeeb u8 stgr; 546c92544dSBjoern A. Zeeb u8 min_crpn; 556c92544dSBjoern A. Zeeb u8 max_crpn; 566c92544dSBjoern A. Zeeb u8 min_crpr; 576c92544dSBjoern A. Zeeb u8 min_pw; 586c92544dSBjoern A. Zeeb u32 min_pri; 596c92544dSBjoern A. Zeeb u32 max_pri; 606c92544dSBjoern A. Zeeb u8 max_pw; 616c92544dSBjoern A. Zeeb u8 min_crbn; 626c92544dSBjoern A. Zeeb u8 max_crbn; 636c92544dSBjoern A. Zeeb u8 min_stgpn; 646c92544dSBjoern A. Zeeb u8 max_stgpn; 656c92544dSBjoern A. Zeeb u8 min_stgpr; 666c92544dSBjoern A. Zeeb u8 rsv[2]; 676c92544dSBjoern A. Zeeb u32 min_stgpr_diff; 686c92544dSBjoern A. Zeeb } __packed; 696c92544dSBjoern A. Zeeb 706c92544dSBjoern A. Zeeb struct mt7915_dfs_radar_spec { 716c92544dSBjoern A. Zeeb struct mt7915_dfs_pulse pulse_th; 726c92544dSBjoern A. Zeeb struct mt7915_dfs_pattern radar_pattern[16]; 736c92544dSBjoern A. Zeeb }; 746c92544dSBjoern A. Zeeb 756c92544dSBjoern A. Zeeb #endif 76