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Searched refs:CSR_WRITE_4 (Results 1 – 25 of 54) sorted by relevance

123

/freebsd/sys/dev/et/
H A Dif_et.c308 CSR_WRITE_4(sc, ET_PM, pmcfg); in et_attach()
417 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
421 CSR_WRITE_4(sc, ET_MII_ADDR, val); in et_miibus_readreg()
424 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); in et_miibus_readreg()
448 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
461 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
465 CSR_WRITE_4(sc, ET_MII_ADDR, val); in et_miibus_writereg()
468 CSR_WRITE_4(sc, ET_MII_CTRL, in et_miibus_writereg()
488 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
570 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); in et_miibus_statchg()
[all …]
/freebsd/sys/dev/lge/
H A Dif_lge.c195 CSR_WRITE_4(sc, reg, \
199 CSR_WRITE_4(sc, reg, \
203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| in lge_eeprom_getword()
276 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); in lge_miibus_readreg()
298 CSR_WRITE_4(sc, LGE_GMIICTL, in lge_miibus_writereg()
376 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); in lge_setmulti()
379 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); in lge_setmulti()
380 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); in lge_setmulti()
[all …]
/freebsd/sys/dev/sis/
H A Dif_sis.c118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) macro
195 CSR_WRITE_4(sc, reg, \
199 CSR_WRITE_4(sc, reg, \
203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); in sis_eeprom_idle()
418 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); in sis_read_mac()
419 CSR_WRITE_4(sc, SIS_CSR, 0); in sis_read_mac()
421 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); in sis_read_mac()
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); in sis_read_mac()
[all …]
/freebsd/sys/dev/alc/
H A Dif_alc.c303 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_813x()
330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_816x()
367 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_813x()
393 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_816x()
451 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_miibus_statchg()
483 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_readreg()
489 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_miiext_readreg()
513 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_writereg()
519 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_miiext_writereg()
720 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); in alc_get_macaddr_813x()
[all …]
/freebsd/sys/dev/jme/
H A Dif_jme.c224 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | in jme_miibus_readreg()
255 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | in jme_miibus_writereg()
368 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); in jme_eeprom_read_byte()
543 CSR_WRITE_4(sc, JME_PAR0, in jme_set_macaddr()
545 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); in jme_set_macaddr()
613 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); in jme_map_intr_vector()
614 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); in jme_map_intr_vector()
615 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); in jme_map_intr_vector()
616 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); in jme_map_intr_vector()
1570 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & in jme_setwol()
[all …]
/freebsd/sys/dev/nge/
H A Dif_nge.c245 CSR_WRITE_4(sc, reg, \
249 CSR_WRITE_4(sc, reg, \
253 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
256 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
288 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); in nge_eeprom_idle()
405 CSR_WRITE_4(sc, NGE_MEAR, val); in nge_mii_bitbang_write()
496 CSR_WRITE_4(sc, reg, data); in nge_miibus_writereg()
600 CSR_WRITE_4(sc, NGE_CFG, reg); in nge_miibus_statchg()
605 CSR_WRITE_4(sc, NGE_CSR, reg); in nge_miibus_statchg()
629 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, in nge_miibus_statchg()
[all …]
/freebsd/sys/dev/dc/
H A Dif_dc.c357 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
360 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
383 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_width()
425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_width()
443 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_idle()
463 CSR_WRITE_4(sc, DC_SIO, 0x00000000); in dc_eeprom_idle()
515 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); in dc_eeprom_getword_pnic()
539 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); in dc_eeprom_getword_xircom()
542 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); in dc_eeprom_getword_xircom()
561 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_getword()
[all …]
H A Ddcphy.c74 CSR_WRITE_4(sc, reg, \
78 CSR_WRITE_4(sc, reg, \
155 CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); in dcphy_attach()
156 CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); in dcphy_attach()
224 CSR_WRITE_4(dc_sc, DC_NETCFG, mode); in dcphy_service()
241 CSR_WRITE_4(dc_sc, DC_NETCFG, mode); in dcphy_service()
385 CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); in dcphy_auto()
387 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF); in dcphy_auto()
/freebsd/sys/dev/bge/
H A Dif_bge.c612 CSR_WRITE_4(sc, off, val); in bge_writemem_direct()
621 CSR_WRITE_4(sc, off, val); in bge_writembx()
963 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); in bge_nvram_getbyte()
974 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); in bge_nvram_getbyte()
976 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); in bge_nvram_getbyte()
977 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); in bge_nvram_getbyte()
997 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); in bge_nvram_getbyte()
1000 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); in bge_nvram_getbyte()
1047 CSR_WRITE_4(sc, BGE_EE_ADDR, in bge_eeprom_getbyte()
1052 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); in bge_eeprom_getbyte()
[all …]
/freebsd/sys/dev/bfe/
H A Dif_bfe.c674 CSR_WRITE_4(sc, BFE_RXCONF, flow); in bfe_miibus_statchg()
681 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); in bfe_miibus_statchg()
684 CSR_WRITE_4(sc, BFE_TX_CTRL, val); in bfe_miibus_statchg()
745 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); in bfe_list_rx_init()
861 CSR_WRITE_4(sc, BFE_SBINTVEC, val); in bfe_pci_setup()
865 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); in bfe_pci_setup()
877 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); in bfe_clear_stats()
904 CSR_WRITE_4(sc, BFE_IMASK, 0); in bfe_chip_halt()
907 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); in bfe_chip_halt()
910 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); in bfe_chip_halt()
[all …]
/freebsd/sys/dev/sge/
H A Dif_sge.c180 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val) macro
215 CSR_WRITE_4(sc, ROMInterface, in sge_read_eeprom()
336 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) | in sge_miibus_readreg()
360 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) | in sge_miibus_writereg()
434 CSR_WRITE_4(sc, StationControl, ctl); in sge_miibus_statchg()
436 CSR_WRITE_4(sc, RGMIIDelay, 0x0441); in sge_miibus_statchg()
437 CSR_WRITE_4(sc, RGMIIDelay, 0x0440); in sge_miibus_statchg()
480 CSR_WRITE_4(sc, RxHashTable, hashes[0]); in sge_rxfilter()
481 CSR_WRITE_4(sc, RxHashTable2, hashes[1]); in sge_rxfilter()
507 CSR_WRITE_4(sc, IntrMask, 0); in sge_reset()
[all …]
/freebsd/sys/dev/my/
H A Dif_my.c140 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
141 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
184 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
202 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
205 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
236 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_readreg()
245 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_readreg()
254 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_readreg()
280 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_writereg()
[all …]
/freebsd/sys/dev/ale/
H A Dif_ale.c209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in ale_miibus_readreg()
235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in ale_miibus_writereg()
292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); in ale_miibus_statchg()
366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); in ale_get_macaddr()
374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
1474 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); in ale_setwol()
1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); in ale_setwol()
1496 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); in ale_setwol()
1504 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); in ale_setwol()
1510 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); in ale_setwol()
[all …]
/freebsd/sys/dev/ti/
H A Dif_ti.c434 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); in ti_mem_read()
463 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); in ti_mem_write()
490 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); in ti_mem_zero()
560 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); in ti_copy_mem()
633 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); in ti_copy_mem()
690 CSR_WRITE_4(sc, TI_WINBASE, origwin); in ti_copy_mem()
727 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); in ti_copy_scratch()
778 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), in ti_copy_scratch()
849 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); in ti_loadfw()
870 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); in ti_loadfw()
[all …]
/freebsd/sys/dev/bwi/
H A Dbwimac.c125 CSR_WRITE_4(sc, BWI_MAC_TMPLT_CTRL, ofs); in bwi_tmplt_write_4()
126 CSR_WRITE_4(sc, BWI_MAC_TMPLT_DATA, val); in bwi_tmplt_write_4()
173 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_read_2()
187 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_read_4()
191 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, in bwi_memobj_read_4()
197 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_read_4()
216 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_write_2()
229 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_write_4()
232 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, in bwi_memobj_write_4()
236 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_write_4()
[all …]
/freebsd/sys/dev/age/
H A Dif_age.c215 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in age_miibus_readreg()
244 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in age_miibus_writereg()
344 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); in age_get_macaddr()
352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
386 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); in age_phy_reset()
388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); in age_phy_reset()
1310 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); in age_setwol()
1403 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); in age_setwol()
1411 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_setwol()
1863 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_ioctl()
[all …]
/freebsd/sys/dev/msk/
H A Dif_msk.c549 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); in msk_miibus_statchg()
633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_setvlan()
635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_setvlan()
638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_setvlan()
640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_setvlan()
1255 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); in msk_phy_power()
1300 CSR_WRITE_4(sc, B2_GP_IO, val); in msk_phy_power()
1358 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); in mskc_reset()
1367 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); in mskc_reset()
1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); in mskc_reset()
[all …]
/freebsd/sys/dev/ipw/
H A Dif_ipwreg.h341 #define CSR_WRITE_4(sc, reg, val) \ macro
352 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
356 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
360 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
365 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
370 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
371 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
375 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
H A Dif_ipw.c1296 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); in ipw_rx_intr()
1386 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); in ipw_intr()
1389 CSR_WRITE_4(sc, IPW_CSR_INTR, r); in ipw_intr()
1406 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); in ipw_intr()
1530 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); in ipw_cmd()
1685 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); in ipw_tx_start()
1800 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); in ipw_stop_master()
1802 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); in ipw_stop_master()
1812 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); in ipw_stop_master()
1828 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); in ipw_reset()
[all …]
/freebsd/sys/dev/stge/
H A Dif_stge.c987 CSR_WRITE_4(sc, STGE_AsicCtrl, in stge_setwol()
1204 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); in stge_start_locked()
1382 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_link_task()
1387 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); in stge_link_task()
1427 CSR_WRITE_4(sc, STGE_MACCtrl, in stge_tx_error()
1479 CSR_WRITE_4(sc, STGE_DMACtrl, in stge_intr()
1921 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); in stge_reset()
1944 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); in stge_reset()
2015 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); in stge_init_locked()
2016 CSR_WRITE_4(sc, STGE_StatisticsMask, in stge_init_locked()
[all …]
/freebsd/sys/dev/iwi/
H A Dif_iwi.c250 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); in MEM_READ_1()
257 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); in MEM_READ_4()
1247 CSR_WRITE_4(sc, data->reg, data->physaddr); in iwi_frame_intr()
1603 CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw); in iwi_rx_intr()
1670 CSR_WRITE_4(sc, IWI_CSR_INTR, r); in iwi_intr()
1744 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur); in iwi_cmd()
1923 CSR_WRITE_4(sc, txq->csr_widx, txq->cur); in iwi_tx_start()
2080 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); in iwi_stop_master()
2082 CSR_WRITE_4(sc, IWI_CSR_RST, IWI_RST_STOP_MASTER); in iwi_stop_master()
2092 CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_PRINCETON_RESET); in iwi_stop_master()
[all …]
H A Dif_iwireg.h591 #define CSR_WRITE_4(sc, reg, val) \ macro
602 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
607 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
612 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
613 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
617 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
/freebsd/sys/dev/rl/
H A Dif_rl.c556 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); in rl_rxfilter()
557 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); in rl_rxfilter()
558 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); in rl_rxfilter()
1059 CSR_WRITE_4(sc, in rl_list_tx_init()
1269 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); in rl_txeof()
1320 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); in rl_twister_update()
1321 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); in rl_twister_update()
1322 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); in rl_twister_update()
1345 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); in rl_twister_update()
1346 CSR_WRITE_4(sc, RL_PARA7C, in rl_twister_update()
[all …]
/freebsd/sys/dev/re/
H A Dif_re.c462 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); in re_gmii_readreg()
493 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | in re_gmii_writereg()
725 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); in re_set_rxmode()
726 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); in re_set_rxmode()
727 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); in re_set_rxmode()
2472 CSR_WRITE_4(sc, RL_TIMERCNT, 1); in re_txeof()
2687 CSR_WRITE_4(sc, RL_TIMERCNT, 1); in re_intr_msi()
2949 CSR_WRITE_4(sc, RL_TIMERCNT, 1); in re_start_locked()
2987 CSR_WRITE_4(sc, RL_TIMERCNT, 1); in re_start_locked()
3015 CSR_WRITE_4(sc, RL_TIMERCNT, 1); in re_start_tx()
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgevar.h216 #define CSR_WRITE_4(sc, reg, val) \ macro
235 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
242 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

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