180 #define	CSR_WRITE_4(sc, reg, val)	bus_write_4(sc->sge_res, reg, val)  macro
215 	CSR_WRITE_4(sc, ROMInterface,  in sge_read_eeprom()
336 	CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |  in sge_miibus_readreg()
360 	CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |  in sge_miibus_writereg()
434 	CSR_WRITE_4(sc, StationControl, ctl);  in sge_miibus_statchg()
436 		CSR_WRITE_4(sc, RGMIIDelay, 0x0441);  in sge_miibus_statchg()
437 		CSR_WRITE_4(sc, RGMIIDelay, 0x0440);  in sge_miibus_statchg()
480 	CSR_WRITE_4(sc, RxHashTable, hashes[0]);  in sge_rxfilter()
481 	CSR_WRITE_4(sc, RxHashTable2, hashes[1]);  in sge_rxfilter()
507 	CSR_WRITE_4(sc, IntrMask, 0);  in sge_reset()
508 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);  in sge_reset()
511 	CSR_WRITE_4(sc, IntrControl, 0x8000);  in sge_reset()
514 	CSR_WRITE_4(sc, IntrControl, 0);  in sge_reset()
516 	CSR_WRITE_4(sc, TX_CTL, 0x1a00);  in sge_reset()
517 	CSR_WRITE_4(sc, RX_CTL, 0x1a00);  in sge_reset()
519 	CSR_WRITE_4(sc, IntrMask, 0);  in sge_reset()
520 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);  in sge_reset()
522 	CSR_WRITE_4(sc, GMIIControl, 0);  in sge_reset()
1337 	CSR_WRITE_4(sc, IntrStatus, status);  in sge_intr()
1339 	CSR_WRITE_4(sc, IntrMask, 0);  in sge_intr()
1356 				CSR_WRITE_4(sc, RX_CTL,  in sge_intr()
1365 		CSR_WRITE_4(sc, IntrStatus, status);  in sge_intr()
1369 		CSR_WRITE_4(sc, IntrMask, SGE_INTRS);  in sge_intr()
1597 		CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB | TX_CTL_POLL);  in sge_start_locked()
1643 	CSR_WRITE_4(sc, TX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_tx_paddr));  in sge_init_locked()
1644 	CSR_WRITE_4(sc, RX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_rx_paddr));  in sge_init_locked()
1646 	CSR_WRITE_4(sc, TxMacControl, 0x60);  in sge_init_locked()
1647 	CSR_WRITE_4(sc, RxWakeOnLan, 0);  in sge_init_locked()
1648 	CSR_WRITE_4(sc, RxWakeOnLanData, 0);  in sge_init_locked()
1666 		CSR_WRITE_4(sc, StationControl, 0x04008001);  in sge_init_locked()
1668 		CSR_WRITE_4(sc, StationControl, 0x04000001);  in sge_init_locked()
1672 	CSR_WRITE_4(sc, IntrControl, 0x08880000);  in sge_init_locked()
1675 		CSR_WRITE_4(sc, IntrControl, sc->sge_intrcontrol);  in sge_init_locked()
1677 		CSR_WRITE_4(sc, IntrTimer, sc->sge_intrtimer);  in sge_init_locked()
1683 	CSR_WRITE_4(sc, IntrStatus, 0xFFFFFFFF);  in sge_init_locked()
1684 	CSR_WRITE_4(sc, IntrMask, SGE_INTRS);  in sge_init_locked()
1687 	CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB);  in sge_init_locked()
1688 	CSR_WRITE_4(sc, RX_CTL, 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);  in sge_init_locked()
1881 	CSR_WRITE_4(sc, IntrMask, 0);  in sge_stop()
1883 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);  in sge_stop()
1885 	CSR_WRITE_4(sc, TX_CTL, 0x1a00);  in sge_stop()
1886 	CSR_WRITE_4(sc, RX_CTL, 0x1a00);  in sge_stop()
1889 	CSR_WRITE_4(sc, IntrMask, 0);  in sge_stop()
1890 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);  in sge_stop()