Lines Matching refs:CSR_WRITE_4
987 CSR_WRITE_4(sc, STGE_AsicCtrl, in stge_setwol()
1204 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); in stge_start_locked()
1382 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_link_task()
1387 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); in stge_link_task()
1427 CSR_WRITE_4(sc, STGE_MACCtrl, in stge_tx_error()
1479 CSR_WRITE_4(sc, STGE_DMACtrl, in stge_intr()
1921 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); in stge_reset()
1944 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); in stge_reset()
2015 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); in stge_init_locked()
2016 CSR_WRITE_4(sc, STGE_StatisticsMask, in stge_init_locked()
2030 CSR_WRITE_4(sc, STGE_TFDListPtrHi, in stge_init_locked()
2032 CSR_WRITE_4(sc, STGE_TFDListPtrLo, in stge_init_locked()
2035 CSR_WRITE_4(sc, STGE_RFDListPtrHi, in stge_init_locked()
2037 CSR_WRITE_4(sc, STGE_RFDListPtrLo, in stge_init_locked()
2071 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, in stge_init_locked()
2092 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); in stge_init_locked()
2116 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); in stge_init_locked()
2135 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_init_locked()
2185 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_vlan_setup()
2219 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_stop()
2225 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); in stge_stop()
2226 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); in stge_stop()
2227 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); in stge_stop()
2228 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); in stge_stop()
2274 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_start_tx()
2296 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_start_rx()
2318 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_stop_tx()
2339 CSR_WRITE_4(sc, STGE_MACCtrl, v); in stge_stop_rx()
2534 CSR_WRITE_4(sc, STGE_HashTable0, 0); in stge_set_multi()
2535 CSR_WRITE_4(sc, STGE_HashTable1, 0); in stge_set_multi()
2553 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); in stge_set_multi()
2554 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); in stge_set_multi()