Lines Matching refs:CSR_WRITE_4
215 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in age_miibus_readreg()
244 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in age_miibus_writereg()
344 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); in age_get_macaddr()
352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
386 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); in age_phy_reset()
388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); in age_phy_reset()
1310 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); in age_setwol()
1403 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); in age_setwol()
1411 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_setwol()
1863 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_ioctl()
1937 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_mac_config()
1981 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | in age_link_task()
1984 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_link_task()
2101 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); in age_intr()
2175 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); in age_int_task()
2511 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); in age_reset()
2523 CSR_WRITE_4(sc, 0x12FC, 0x6500); in age_reset()
2524 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); in age_reset()
2581 CSR_WRITE_4(sc, AGE_PAR0, in age_init_locked()
2583 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); in age_init_locked()
2587 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); in age_init_locked()
2589 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2591 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2593 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2595 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2597 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2599 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, in age_init_locked()
2604 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, in age_init_locked()
2608 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); in age_init_locked()
2624 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, in age_init_locked()
2631 CSR_WRITE_4(sc, AGE_HDPX_CFG, in age_init_locked()
2649 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); in age_init_locked()
2662 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); in age_init_locked()
2665 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, in age_init_locked()
2679 CSR_WRITE_4(sc, 0x12FC, 0x6500); in age_init_locked()
2684 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); in age_init_locked()
2720 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, in age_init_locked()
2725 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, in age_init_locked()
2732 CSR_WRITE_4(sc, AGE_RXQ_CFG, in age_init_locked()
2742 CSR_WRITE_4(sc, AGE_TXQ_CFG, in age_init_locked()
2751 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, in age_init_locked()
2757 CSR_WRITE_4(sc, AGE_DMA_CFG, in age_init_locked()
2763 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, in age_init_locked()
2770 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, in age_init_locked()
2774 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); in age_init_locked()
2775 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); in age_init_locked()
2781 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); in age_init_locked()
2790 CSR_WRITE_4(sc, AGE_MAC_CFG, in age_init_locked()
2804 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); in age_init_locked()
2805 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); in age_init_locked()
2808 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); in age_init_locked()
2842 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); in age_stop()
2843 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); in age_stop()
2845 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); in age_stop()
2850 CSR_WRITE_4(sc, AGE_DMA_CFG, in age_stop()
2853 CSR_WRITE_4(sc, AGE_TXQ_CFG, in age_stop()
2855 CSR_WRITE_4(sc, AGE_RXQ_CFG, in age_stop()
2908 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_stop_txmac()
2914 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); in age_stop_txmac()
2937 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_stop_rxmac()
2943 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); in age_stop_rxmac()
3111 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_rxvlan()
3146 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); in age_rxfilter()
3147 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); in age_rxfilter()
3148 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); in age_rxfilter()
3156 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); in age_rxfilter()
3157 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); in age_rxfilter()
3158 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); in age_rxfilter()