Lines Matching refs:CSR_WRITE_4
674 CSR_WRITE_4(sc, BFE_RXCONF, flow); in bfe_miibus_statchg()
681 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); in bfe_miibus_statchg()
684 CSR_WRITE_4(sc, BFE_TX_CTRL, val); in bfe_miibus_statchg()
745 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); in bfe_list_rx_init()
861 CSR_WRITE_4(sc, BFE_SBINTVEC, val); in bfe_pci_setup()
865 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); in bfe_pci_setup()
877 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); in bfe_clear_stats()
904 CSR_WRITE_4(sc, BFE_IMASK, 0); in bfe_chip_halt()
907 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); in bfe_chip_halt()
910 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); in bfe_chip_halt()
911 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); in bfe_chip_halt()
930 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); in bfe_chip_reset()
931 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); in bfe_chip_reset()
933 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); in bfe_chip_reset()
937 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); in bfe_chip_reset()
950 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); in bfe_chip_reset()
955 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); in bfe_chip_reset()
967 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & in bfe_chip_reset()
977 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); in bfe_chip_reset()
978 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); in bfe_chip_reset()
981 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); in bfe_chip_reset()
987 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); in bfe_chip_reset()
988 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); in bfe_chip_reset()
990 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | in bfe_chip_reset()
992 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); in bfe_chip_reset()
1008 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); in bfe_core_disable()
1011 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | in bfe_core_disable()
1016 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); in bfe_core_disable()
1029 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); in bfe_core_reset()
1035 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); in bfe_core_reset()
1038 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); in bfe_core_reset()
1041 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); in bfe_core_reset()
1046 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); in bfe_core_reset()
1060 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); in bfe_cam_write()
1064 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); in bfe_cam_write()
1065 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | in bfe_cam_write()
1100 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); in bfe_set_rx_mode()
1110 CSR_WRITE_4(sc, BFE_RXCONF, val); in bfe_set_rx_mode()
1186 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); in bfe_readphy()
1187 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | in bfe_readphy()
1203 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); in bfe_writephy()
1204 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | in bfe_writephy()
1247 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); in bfe_stats_update()
1452 CSR_WRITE_4(sc, BFE_ISTAT, istat); in bfe_intr()
1646 CSR_WRITE_4(sc, BFE_DMATX_PTR, in bfe_start_locked()
1659 CSR_WRITE_4(sc, BFE_DMATX_PTR, in bfe_start_locked()
1707 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); in bfe_init_locked()