Lines Matching refs:CSR_WRITE_4
303 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_813x()
330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_816x()
367 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_813x()
393 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_816x()
451 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_miibus_statchg()
483 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_readreg()
489 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_miiext_readreg()
513 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_writereg()
519 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_miiext_writereg()
720 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); in alc_get_macaddr_813x()
745 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, in alc_get_macaddr_813x()
747 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); in alc_get_macaddr_813x()
750 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | in alc_get_macaddr_813x()
771 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); in alc_get_macaddr_813x()
815 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); in alc_get_macaddr_816x()
842 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | in alc_get_macaddr_816x()
887 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); in alc_disable_l0s_l1()
1031 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); in alc_phy_reset_816x()
1033 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); in alc_phy_reset_816x()
1054 CSR_WRITE_4(sc, ALC_LPI_CTL, val); in alc_phy_reset_816x()
1107 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); in alc_phy_down()
1232 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); in alc_aspm_813x()
1267 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); in alc_aspm_816x()
1280 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); in alc_init_pcie()
1283 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, in alc_init_pcie()
1285 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, in alc_init_pcie()
1295 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); in alc_init_pcie()
1324 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); in alc_init_pcie()
1331 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); in alc_init_pcie()
1338 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); in alc_init_pcie()
1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | in alc_config_msi()
1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | in alc_config_msi()
1371 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); in alc_config_msi()
2539 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); in alc_setwol_813x()
2542 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); in alc_setwol_813x()
2545 CSR_WRITE_4(sc, ALC_MASTER_CFG, in alc_setwol_813x()
2553 CSR_WRITE_4(sc, ALC_MASTER_CFG, in alc_setwol_813x()
2560 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); in alc_setwol_813x()
2568 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_setwol_813x()
2572 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); in alc_setwol_813x()
2576 CSR_WRITE_4(sc, ALC_MASTER_CFG, in alc_setwol_813x()
2600 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); in alc_setwol_816x()
2612 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); in alc_setwol_816x()
2627 CSR_WRITE_4(sc, ALC_MISC, reg); in alc_setwol_816x()
2629 CSR_WRITE_4(sc, ALC_MISC, reg); in alc_setwol_816x()
2630 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); in alc_setwol_816x()
2631 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); in alc_setwol_816x()
2632 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); in alc_setwol_816x()
2635 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); in alc_setwol_816x()
2983 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, in alc_start_tx()
3164 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_mac_config()
3332 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); in alc_intr()
3359 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); in alc_int_task()
3406 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); in alc_int_task()
3408 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); in alc_int_task()
3579 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, in alc_rxintr()
3779 CSR_WRITE_4(sc, ALC_MISC3, reg); in alc_osc_reset()
3790 CSR_WRITE_4(sc, ALC_MISC, reg); in alc_osc_reset()
3791 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); in alc_osc_reset()
3794 CSR_WRITE_4(sc, ALC_MISC2, reg); in alc_osc_reset()
3795 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); in alc_osc_reset()
3802 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); in alc_osc_reset()
3803 CSR_WRITE_4(sc, ALC_MISC, reg); in alc_osc_reset()
3818 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); in alc_reset()
3827 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); in alc_reset()
3833 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); in alc_reset()
3867 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); in alc_reset()
3871 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); in alc_reset()
3878 CSR_WRITE_4(sc, ALC_MISC3, reg); in alc_reset()
3883 CSR_WRITE_4(sc, ALC_MISC, reg); in alc_reset()
3889 CSR_WRITE_4(sc, ALC_SERDES_LOCK, in alc_reset()
3941 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | in alc_init_locked()
3946 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, in alc_init_locked()
3949 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); in alc_init_locked()
3953 CSR_WRITE_4(sc, ALC_PAR0, in alc_init_locked()
3955 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); in alc_init_locked()
3961 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); in alc_init_locked()
3964 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); in alc_init_locked()
3965 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); in alc_init_locked()
3967 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); in alc_init_locked()
3969 CSR_WRITE_4(sc, ALC_TD_RING_CNT, in alc_init_locked()
3973 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); in alc_init_locked()
3974 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); in alc_init_locked()
3977 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); in alc_init_locked()
3978 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); in alc_init_locked()
3979 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); in alc_init_locked()
3982 CSR_WRITE_4(sc, ALC_RD_RING_CNT, in alc_init_locked()
4000 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); in alc_init_locked()
4004 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); in alc_init_locked()
4007 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); in alc_init_locked()
4008 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); in alc_init_locked()
4009 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); in alc_init_locked()
4012 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, in alc_init_locked()
4015 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); in alc_init_locked()
4017 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); in alc_init_locked()
4018 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); in alc_init_locked()
4022 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); in alc_init_locked()
4023 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); in alc_init_locked()
4024 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); in alc_init_locked()
4025 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); in alc_init_locked()
4026 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); in alc_init_locked()
4027 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); in alc_init_locked()
4028 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); in alc_init_locked()
4029 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); in alc_init_locked()
4033 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); in alc_init_locked()
4039 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); in alc_init_locked()
4052 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); in alc_init_locked()
4057 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); in alc_init_locked()
4060 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); in alc_init_locked()
4061 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, in alc_init_locked()
4065 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); in alc_init_locked()
4066 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); in alc_init_locked()
4068 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); in alc_init_locked()
4076 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); in alc_init_locked()
4094 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); in alc_init_locked()
4098 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); in alc_init_locked()
4101 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, in alc_init_locked()
4111 CSR_WRITE_4(sc, ALC_HDPX_CFG, in alc_init_locked()
4131 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); in alc_init_locked()
4141 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); in alc_init_locked()
4147 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); in alc_init_locked()
4153 CSR_WRITE_4(sc, ALC_WRR, reg); in alc_init_locked()
4156 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, in alc_init_locked()
4177 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, in alc_init_locked()
4188 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, in alc_init_locked()
4197 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); in alc_init_locked()
4198 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); in alc_init_locked()
4216 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); in alc_init_locked()
4248 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); in alc_init_locked()
4275 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_init_locked()
4282 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); in alc_init_locked()
4283 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); in alc_init_locked()
4284 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); in alc_init_locked()
4316 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); in alc_stop()
4317 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); in alc_stop()
4322 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); in alc_stop()
4327 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); in alc_stop()
4372 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_stop_mac()
4406 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); in alc_start_queue()
4410 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); in alc_start_queue()
4424 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); in alc_stop_queue()
4429 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); in alc_stop_queue()
4436 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); in alc_stop_queue()
4503 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); in alc_init_rx_ring()
4565 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_rxvlan()
4609 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); in alc_rxfilter()
4610 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); in alc_rxfilter()
4611 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); in alc_rxfilter()