Lines Matching refs:CSR_WRITE_4
195 CSR_WRITE_4(sc, reg, \
199 CSR_WRITE_4(sc, reg, \
203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| in lge_eeprom_getword()
276 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); in lge_miibus_readreg()
298 CSR_WRITE_4(sc, LGE_GMIICTL, in lge_miibus_writereg()
376 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); in lge_setmulti()
379 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); in lge_setmulti()
380 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); in lge_setmulti()
385 CSR_WRITE_4(sc, LGE_MAR0, 0); in lge_setmulti()
386 CSR_WRITE_4(sc, LGE_MAR1, 0); in lge_setmulti()
391 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); in lge_setmulti()
392 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); in lge_setmulti()
639 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); in lge_list_rx_init()
716 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); in lge_newbuf()
998 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); in lge_tick()
1000 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); in lge_tick()
1071 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); in lge_intr()
1120 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); in lge_encap()
1217 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[0])); in lge_init_locked()
1218 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[4])); in lge_init_locked()
1234 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| in lge_init_locked()
1241 CSR_WRITE_4(sc, LGE_MODE1, in lge_init_locked()
1244 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); in lge_init_locked()
1251 CSR_WRITE_4(sc, LGE_MODE1, in lge_init_locked()
1254 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); in lge_init_locked()
1258 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); in lge_init_locked()
1261 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); in lge_init_locked()
1264 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); in lge_init_locked()
1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); in lge_init_locked()
1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); in lge_init_locked()
1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); in lge_init_locked()
1274 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); in lge_init_locked()
1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| in lge_init_locked()
1282 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); in lge_init_locked()
1293 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| in lge_init_locked()
1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); in lge_init_locked()
1304 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); in lge_init_locked()
1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); in lge_init_locked()
1307 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); in lge_init_locked()
1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); in lge_init_locked()
1313 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| in lge_init_locked()
1403 CSR_WRITE_4(sc, LGE_MODE1, in lge_ioctl()
1409 CSR_WRITE_4(sc, LGE_MODE1, in lge_ioctl()
1477 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); in lge_stop()
1480 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); in lge_stop()