Lines Matching refs:CSR_WRITE_4
357 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
360 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
383 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_width()
425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_width()
443 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_idle()
463 CSR_WRITE_4(sc, DC_SIO, 0x00000000); in dc_eeprom_idle()
515 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); in dc_eeprom_getword_pnic()
539 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); in dc_eeprom_getword_xircom()
542 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); in dc_eeprom_getword_xircom()
561 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_getword()
628 CSR_WRITE_4(sc, DC_SIO, val); in dc_mii_bitbang_write()
684 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | in dc_miibus_readreg()
698 CSR_WRITE_4(sc, DC_ROM, in dc_miibus_readreg()
751 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); in dc_miibus_readreg()
755 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); in dc_miibus_readreg()
769 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | in dc_miibus_writereg()
779 CSR_WRITE_4(sc, DC_ROM, in dc_miibus_writereg()
818 CSR_WRITE_4(sc, phy_reg, data); in dc_miibus_writereg()
824 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); in dc_miibus_writereg()
828 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); in dc_miibus_writereg()
1019 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); in dc_setfilt_21143()
1078 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | in dc_setfilt_admtek()
1080 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); in dc_setfilt_admtek()
1094 CSR_WRITE_4(sc, DC_AL_MAR0, 0); in dc_setfilt_admtek()
1095 CSR_WRITE_4(sc, DC_AL_MAR1, 0); in dc_setfilt_admtek()
1110 CSR_WRITE_4(sc, DC_AL_MAR0, ctx.hashes[0]); in dc_setfilt_admtek()
1111 CSR_WRITE_4(sc, DC_AL_MAR1, ctx.hashes[1]); in dc_setfilt_admtek()
1125 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); in dc_setfilt_asix()
1126 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); in dc_setfilt_asix()
1127 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); in dc_setfilt_asix()
1128 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); in dc_setfilt_asix()
1151 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); in dc_setfilt_asix()
1152 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); in dc_setfilt_asix()
1153 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); in dc_setfilt_asix()
1154 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); in dc_setfilt_asix()
1166 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); in dc_setfilt_asix()
1167 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); in dc_setfilt_asix()
1168 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); in dc_setfilt_asix()
1169 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); in dc_setfilt_asix()
1240 CSR_WRITE_4(sc, DC_NETCFG, in dc_setfilt_uli()
1246 CSR_WRITE_4(sc, DC_NETCFG, in dc_setfilt_uli()
1249 CSR_WRITE_4(sc, DC_NETCFG, filter); in dc_setfilt_uli()
1255 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); in dc_setfilt_uli()
1331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); in dc_setfilt_xircom()
1416 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); in dc_setcfg()
1449 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); in dc_setcfg()
1538 CSR_WRITE_4(sc, DC_IMR, 0x00000000); in dc_reset()
1539 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); in dc_reset()
1540 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); in dc_reset()
1550 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); in dc_reset()
1551 CSR_WRITE_4(sc, DC_WATCHDOG, 0); in dc_reset()
1620 CSR_WRITE_4(sc, DC_WATCHDOG, reg); in dc_apply_fixup()
1625 CSR_WRITE_4(sc, DC_WATCHDOG, reg); in dc_apply_fixup()
2327 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); in dc_attach()
2328 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); in dc_attach()
2329 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); in dc_attach()
2330 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); in dc_attach()
2331 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); in dc_attach()
2332 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); in dc_attach()
2333 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); in dc_attach()
2337 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); in dc_attach()
2338 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); in dc_attach()
2412 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | in dc_attach()
2415 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | in dc_attach()
3184 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); in dc_tx_underrun()
3205 CSR_WRITE_4(sc, DC_NETCFG, netcfg); in dc_tx_underrun()
3207 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); in dc_tx_underrun()
3249 CSR_WRITE_4(sc, DC_ISR, status); in dc_poll()
3260 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); in dc_poll()
3303 CSR_WRITE_4(sc, DC_IMR, 0x00000000); in dc_intr()
3309 CSR_WRITE_4(sc, DC_ISR, status); in dc_intr()
3325 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); in dc_intr()
3358 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); in dc_intr()
3564 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); in dc_start_locked()
3611 CSR_WRITE_4(sc, DC_BUSCTL, 0); in dc_init_locked()
3613 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); in dc_init_locked()
3677 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | in dc_init_locked()
3680 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | in dc_init_locked()
3704 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); in dc_init_locked()
3705 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); in dc_init_locked()
3717 CSR_WRITE_4(sc, DC_IMR, 0x00000000); in dc_init_locked()
3720 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); in dc_init_locked()
3721 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); in dc_init_locked()
3725 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | in dc_init_locked()
3737 CSR_WRITE_4(sc, DC_WATCHDOG, in dc_init_locked()
3739 CSR_WRITE_4(sc, DC_WATCHDOG, 0); in dc_init_locked()
3752 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); in dc_init_locked()
3894 CSR_WRITE_4(sc, DC_IMR, 0x00000000); in dc_ioctl()
3904 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); in dc_ioctl()
3971 CSR_WRITE_4(sc, DC_NETCFG, in dc_stop()
3973 CSR_WRITE_4(sc, DC_IMR, 0x00000000); in dc_stop()
3978 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); in dc_stop()
3979 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); in dc_stop()