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Searched +full:zynqmp +full:- +full:firmware (Results 1 – 25 of 44) sorted by relevance

12

/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
[all …]
/linux/Documentation/devicetree/bindings/crypto/
H A Dxlnx,zynqmp-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator
10 - Kalyani Akula <kalyani.akula@amd.com>
11 - Michal Simek <michal.simek@amd.com>
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
22 - compatible
[all …]
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
16 firmware interface.
20 const: xlnx,zynqmp-pcap-fpga
23 - compatible
28 - |
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
23 - items:
24 - enum:
[all …]
/linux/drivers/firmware/xilinx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
13 Firmware interface driver is used by different
14 drivers to communicate with the firmware for
16 Say yes to enable ZynqMP firmware interface driver.
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
23 Say yes to enable ZynqMP firmware interface debug APIs.
H A Dzynqmp-debug.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
5 * Copyright (C) 2014-2018 Xilinx, Inc.
6 * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc.
20 #include <linux/firmware/xlnx-zynqmp.h>
21 #include "zynqmp-debug.h"
64 * zynqmp_pm_ioctl - PM IOCTL for device control and configs
81 * zynqmp_pm_argument_value() - Extract argument value from a PM-API request
82 * @arg: Entered PM-API argument in string format
101 * get_pm_api_id() - Extract API-ID from a PM-API request
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H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
28 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/firmware/xlnx-event-manager.h>
30 #include "zynqmp-debug.h"
37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
[all …]
H A Dzynqmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
3 * Firmware Layer for UFS APIs
8 #include <linux/firmware/xlnx-zynqmp.h>
17 #define TXRX_CFGRDY_OFFSET 0x1054 /* M-PHY TX-RX Config ready */
24 /* Mask to check M-PHY TX-RX configuration readiness */
31 * zynqmp_pm_is_mphy_tx_rx_config_ready - check M-PHY TX-RX config readiness
42 return -EINVAL; in zynqmp_pm_is_mphy_tx_rx_config_ready()
59 * zynqmp_pm_is_sram_init_done - check SRAM initialization
70 return -EINVAL; in zynqmp_pm_is_sram_init_done()
87 * zynqmp_pm_set_sram_bypass - Set SRAM bypass Control
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dxlnx,zynqmp-gpio-modepin.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ZynqMP Mode Pin GPIO controller
10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
15 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
19 const: xlnx,zynqmp-gpio-modepin
21 gpio-controller: true
23 "#gpio-cells":
[all …]
/linux/Documentation/driver-api/xilinx/
H A Deemi.rst5 Xilinx Zynq MPSoC Firmware Interface
6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
9 driver provides an interface to firmware APIs. Interface APIs can be
13 ----------------------------------------------
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
/linux/drivers/clk/zynqmp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
8 Support for the Zynqmp Ultrascale clock controller.
9 It has a dependency on the PMU firmware.
/linux/drivers/fpga/
H A Dzynqmp-fpga.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
51 kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); in zynqmp_fpga_ops_write()
53 return -ENOMEM; in zynqmp_fpga_ops_write()
[all …]
/linux/drivers/nvmem/
H A Dzynqmp_nvmem.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
7 #include <linux/dma-mapping.h>
9 #include <linux/nvmem-provider.h>
12 #include <linux/firmware/xlnx-zynqmp.h>
40 * struct xilinx_efuse - the basic structure
44 * @flag: 0 - represents efuse read and 1- represents efuse write
45 * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
46 * 1 - represents puf user fuse row number.
74 return -EOPNOTSUPP; in zynqmp_efuse_access()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP pin controller
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <linux/firmware/xlnx-zynqmp.h>
22 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
55 * struct zynqmp_pmux_function - a pinmux function
70 * struct zynqmp_pinctrl - driver data
90 * struct zynqmp_pctrl_group - Pin control group info
108 return pctrl->ngroups + zynqmp_desc.npins; in zynqmp_pctrl_get_groups_count()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
46 functionality by firmware, so only a small amount is available
80 will be called pinctrl-apple-gpio.
83 bool "Axis ARTPEC-6 pin controller driver"
88 This is the driver for the Axis ARTPEC-6 pin controller. This driver
91 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
100 functionality. This driver supports the pinmux, push-pull and
129 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
153 The Awinic AW9523/AW9523B is a multi-function I2C GPIO
180 called pinctrl-cy8c95x0.
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,zynqmp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 ZynqMP's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
31 const: xlnx,zynqmp-pinctrl
[all …]
/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP R5 Remote Processor driver
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
[all …]
/linux/drivers/gpio/
H A Dgpio-zynqmp-modepin.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the ps-mode pin configuration.
16 #include <linux/firmware/xlnx-zynqmp.h>
18 /* 4-bit boot mode pins */
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
50 * modepin_gpio_set_value - Modify the state of the pin with specified value
85 * modepin_gpio_dir_in - Set the direction of the specified GPIO pin as input
97 * modepin_gpio_dir_out - Set the direction of the specified GPIO pin as output
111 * modepin_gpio_probe - Initialization method for modepin_gpio
[all …]
/linux/drivers/pmdomain/xilinx/
H A Dzynqmp-pm-domains.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Generic PM domain support
5 * Copyright (C) 2015-2019 Xilinx, Inc.
20 #include <linux/firmware/xlnx-zynqmp.h>
27 * struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
42 * zynqmp_gpd_is_active_wakeup_path() - Check if device is in wakeup source
65 * zynqmp_gpd_power_on() - Power on PM domain
78 ret = zynqmp_pm_set_requirement(pd->node_id, in zynqmp_gpd_power_on()
83 dev_err(&domain->dev, in zynqmp_gpd_power_on()
85 ZYNQMP_PM_CAPABILITY_ACCESS, pd->node_id, ret); in zynqmp_gpd_power_on()
[all …]
/linux/drivers/reset/
H A Dreset-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
13 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
107 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in zynqmp_reset_probe()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
105 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
108 If compiled as module, it will be called reset-gpio.
157 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
166 Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
239 tristate "Raspberry Pi 4 Firmware Reset Driver"
243 Raspberry Pi 4's co-processor controls some of the board's HW
246 interfacing with RPi4's co-processor and model these firmware
270 controlled by firmware that implements the SCMI interface.
[all …]
/linux/drivers/soc/xilinx/
H A Dzynqmp_power.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2019 Xilinx, Inc.
19 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/firmware/xlnx-event-manager.h>
21 #include <linux/mailbox/zynqmp-ipi-message.h>
24 * struct zynqmp_pm_work_struct - Wrapper for struct work_struct
34 * struct zynqmp_pm_event_info - event related information
37 * PM_NOTIFY_CB - for Error Events,
38 * PM_INIT_SUSPEND_CB - for suspend callback.
39 * @node_id: Node-Id related to event.
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-zynqmp-fpga1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
54 BIT(17) System Monitor over-temperature if set
56 BIT(18) to BIT(20) Start-up state machine (0 to 7)

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