1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 23 24if EDAC 25 26config EDAC_LEGACY_SYSFS 27 bool "EDAC legacy sysfs" 28 default y 29 help 30 Enable the compatibility sysfs nodes. 31 Use 'Y' if your edac utilities aren't ported to work with the newer 32 structures. 33 34config EDAC_DEBUG 35 bool "Debugging" 36 select DEBUG_FS 37 help 38 This turns on debugging information for the entire EDAC subsystem. 39 You do so by inserting edac_module with "edac_debug_level=x." Valid 40 levels are 0-4 (from low to high) and by default it is set to 2. 41 Usually you should select 'N' here. 42 43config EDAC_DECODE_MCE 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 45 depends on CPU_SUP_AMD && X86_MCE_AMD 46 default y 47 help 48 Enable this option if you want to decode Machine Check Exceptions 49 occurring on your machine in human-readable form. 50 51 You should definitely say Y here in case you want to decode MCEs 52 which occur really early upon boot, before the module infrastructure 53 has been initialized. 54 55config EDAC_GHES 56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57 depends on ACPI_APEI_GHES 58 select UEFI_CPER 59 help 60 Not all machines support hardware-driven error report. Some of those 61 provide a BIOS-driven error report mechanism via ACPI, using the 62 APEI/GHES driver. By enabling this option, the error reports provided 63 by GHES are sent to userspace via the EDAC API. 64 65 When this option is enabled, it will disable the hardware-driven 66 mechanisms, if a GHES BIOS is detected, entering into the 67 "Firmware First" mode. 68 69 It should be noticed that keeping both GHES and a hardware-driven 70 error mechanism won't work well, as BIOS will race with OS, while 71 reading the error registers. So, if you want to not use "Firmware 72 first" GHES error mechanism, you should disable GHES either at 73 compilation time or by passing "ghes.disable=1" Kernel parameter 74 at boot time. 75 76 In doubt, say 'Y'. 77 78config EDAC_SCRUB 79 bool "EDAC scrub feature" 80 help 81 The EDAC scrub feature is optional and is designed to control the 82 memory scrubbers in the system. The common sysfs scrub interface 83 abstracts the control of various arbitrary scrubbing functionalities 84 into a unified set of functions. 85 Say 'y/n' to enable/disable EDAC scrub feature. 86 87config EDAC_ECS 88 bool "EDAC ECS (Error Check Scrub) feature" 89 help 90 The EDAC ECS feature is optional and is designed to control on-die 91 error check scrub (e.g., DDR5 ECS) in the system. The common sysfs 92 ECS interface abstracts the control of various ECS functionalities 93 into a unified set of functions. 94 Say 'y/n' to enable/disable EDAC ECS feature. 95 96config EDAC_MEM_REPAIR 97 bool "EDAC memory repair feature" 98 help 99 The EDAC memory repair feature is optional and is designed to control 100 the memory devices with repair features, such as Post Package Repair 101 (PPR), memory sparing etc. The common sysfs memory repair interface 102 abstracts the control of various memory repair functionalities into 103 a unified set of functions. 104 Say 'y/n' to enable/disable EDAC memory repair feature. 105 106config EDAC_AMD64 107 tristate "AMD64 (Opteron, Athlon64)" 108 depends on AMD_NB && EDAC_DECODE_MCE 109 depends on AMD_NODE 110 imply AMD_ATL 111 help 112 Support for error detection and correction of DRAM ECC errors on 113 the AMD64 families (>= K8) of memory controllers. 114 115 When EDAC_DEBUG is enabled, hardware error injection facilities 116 through sysfs are available: 117 118 AMD CPUs up to and excluding family 0x17 provide for Memory 119 Error Injection into the ECC detection circuits. The amd64_edac 120 module allows the operator/user to inject Uncorrectable and 121 Correctable errors into DRAM. 122 123 When enabled, in each of the respective memory controller directories 124 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 125 126 - inject_section (0..3, 16-byte section of 64-byte cacheline), 127 - inject_word (0..8, 16-bit word of 16-byte section), 128 - inject_ecc_vector (hex ecc vector: select bits of inject word) 129 130 In addition, there are two control files, inject_read and inject_write, 131 which trigger the DRAM ECC Read and Write respectively. 132 133config EDAC_AL_MC 134 tristate "Amazon's Annapurna Lab Memory Controller" 135 depends on (ARCH_ALPINE || COMPILE_TEST) 136 help 137 Support for error detection and correction for Amazon's Annapurna 138 Labs Alpine chips which allow 1 bit correction and 2 bits detection. 139 140config EDAC_AMD76X 141 tristate "AMD 76x (760, 762, 768)" 142 depends on PCI && X86_32 143 help 144 Support for error detection and correction on the AMD 76x 145 series of chipsets used with the Athlon processor. 146 147config EDAC_E7XXX 148 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 149 depends on PCI && X86_32 150 help 151 Support for error detection and correction on the Intel 152 E7205, E7500, E7501 and E7505 server chipsets. 153 154config EDAC_E752X 155 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 156 depends on PCI && X86 157 help 158 Support for error detection and correction on the Intel 159 E7520, E7525, E7320 server chipsets. 160 161config EDAC_I82443BXGX 162 tristate "Intel 82443BX/GX (440BX/GX)" 163 depends on PCI && X86_32 164 depends on BROKEN 165 help 166 Support for error detection and correction on the Intel 167 82443BX/GX memory controllers (440BX/GX chipsets). 168 169config EDAC_I82875P 170 tristate "Intel 82875p (D82875P, E7210)" 171 depends on PCI && X86_32 172 help 173 Support for error detection and correction on the Intel 174 DP82785P and E7210 server chipsets. 175 176config EDAC_I82975X 177 tristate "Intel 82975x (D82975x)" 178 depends on PCI && X86 179 help 180 Support for error detection and correction on the Intel 181 DP82975x server chipsets. 182 183config EDAC_I3000 184 tristate "Intel 3000/3010" 185 depends on PCI && X86 186 help 187 Support for error detection and correction on the Intel 188 3000 and 3010 server chipsets. 189 190config EDAC_I3200 191 tristate "Intel 3200" 192 depends on PCI && X86 193 help 194 Support for error detection and correction on the Intel 195 3200 and 3210 server chipsets. 196 197config EDAC_IE31200 198 tristate "Intel e312xx" 199 depends on PCI && X86 && X86_MCE_INTEL 200 help 201 Support for error detection and correction on the Intel 202 E3-1200 based DRAM controllers. 203 204config EDAC_X38 205 tristate "Intel X38" 206 depends on PCI && X86 207 help 208 Support for error detection and correction on the Intel 209 X38 server chipsets. 210 211config EDAC_I5400 212 tristate "Intel 5400 (Seaburg) chipsets" 213 depends on PCI && X86 214 help 215 Support for error detection and correction the Intel 216 i5400 MCH chipset (Seaburg). 217 218config EDAC_I7CORE 219 tristate "Intel i7 Core (Nehalem) processors" 220 depends on PCI && X86 && X86_MCE_INTEL 221 help 222 Support for error detection and correction the Intel 223 i7 Core (Nehalem) Integrated Memory Controller that exists on 224 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 225 and Xeon 55xx processors. 226 227config EDAC_I82860 228 tristate "Intel 82860" 229 depends on PCI && X86_32 230 help 231 Support for error detection and correction on the Intel 232 82860 chipset. 233 234config EDAC_R82600 235 tristate "Radisys 82600 embedded chipset" 236 depends on PCI && X86_32 237 help 238 Support for error detection and correction on the Radisys 239 82600 embedded chipset. 240 241config EDAC_I5000 242 tristate "Intel Greencreek/Blackford chipset" 243 depends on X86 && PCI 244 depends on BROKEN 245 help 246 Support for error detection and correction the Intel 247 Greekcreek/Blackford chipsets. 248 249config EDAC_I5100 250 tristate "Intel San Clemente MCH" 251 depends on X86 && PCI 252 help 253 Support for error detection and correction the Intel 254 San Clemente MCH. 255 256config EDAC_I7300 257 tristate "Intel Clarksboro MCH" 258 depends on X86 && PCI 259 help 260 Support for error detection and correction the Intel 261 Clarksboro MCH (Intel 7300 chipset). 262 263config EDAC_SBRIDGE 264 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 265 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 266 help 267 Support for error detection and correction the Intel 268 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 269 270config EDAC_SKX 271 tristate "Intel Skylake server Integrated MC" 272 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 273 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 274 select DMI 275 select ACPI_ADXL 276 help 277 Support for error detection and correction the Intel 278 Skylake server Integrated Memory Controllers. If your 279 system has non-volatile DIMMs you should also manually 280 select CONFIG_ACPI_NFIT. 281 282config EDAC_I10NM 283 tristate "Intel 10nm server Integrated MC" 284 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 285 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 286 select DMI 287 select ACPI_ADXL 288 help 289 Support for error detection and correction the Intel 290 10nm server Integrated Memory Controllers. If your 291 system has non-volatile DIMMs you should also manually 292 select CONFIG_ACPI_NFIT. 293 294config EDAC_PND2 295 tristate "Intel Pondicherry2" 296 depends on PCI && X86_64 && X86_MCE_INTEL 297 select P2SB if X86 298 help 299 Support for error detection and correction on the Intel 300 Pondicherry2 Integrated Memory Controller. This SoC IP is 301 first used on the Apollo Lake platform and Denverton 302 micro-server but may appear on others in the future. 303 304config EDAC_IGEN6 305 tristate "Intel client SoC Integrated MC" 306 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 307 depends on X86_64 && X86_MCE_INTEL 308 help 309 Support for error detection and correction on the Intel 310 client SoC Integrated Memory Controller using In-Band ECC IP. 311 This In-Band ECC is first used on the Elkhart Lake SoC but 312 may appear on others in the future. 313 314config EDAC_MPC85XX 315 bool "Freescale MPC83xx / MPC85xx" 316 depends on FSL_SOC && EDAC=y 317 help 318 Support for error detection and correction on the Freescale 319 MPC8349, MPC8560, MPC8540, MPC8548, T4240 320 321config EDAC_LAYERSCAPE 322 tristate "Freescale Layerscape DDR" 323 depends on ARCH_LAYERSCAPE || SOC_LS1021A 324 help 325 Support for error detection and correction on Freescale memory 326 controllers on Layerscape SoCs. 327 328config EDAC_PASEMI 329 tristate "PA Semi PWRficient" 330 depends on PPC_PASEMI && PCI 331 help 332 Support for error detection and correction on PA Semi 333 PWRficient. 334 335config EDAC_CPC925 336 tristate "IBM CPC925 Memory Controller (PPC970FX)" 337 depends on PPC64 338 help 339 Support for error detection and correction on the 340 IBM CPC925 Bridge and Memory Controller, which is 341 a companion chip to the PowerPC 970 family of 342 processors. 343 344config EDAC_HIGHBANK_MC 345 tristate "Highbank Memory Controller" 346 depends on ARCH_HIGHBANK 347 help 348 Support for error detection and correction on the 349 Calxeda Highbank memory controller. 350 351config EDAC_HIGHBANK_L2 352 tristate "Highbank L2 Cache" 353 depends on ARCH_HIGHBANK 354 help 355 Support for error detection and correction on the 356 Calxeda Highbank memory controller. 357 358config EDAC_OCTEON_PC 359 tristate "Cavium Octeon Primary Caches" 360 depends on CPU_CAVIUM_OCTEON 361 help 362 Support for error detection and correction on the primary caches of 363 the cnMIPS cores of Cavium Octeon family SOCs. 364 365config EDAC_OCTEON_L2C 366 tristate "Cavium Octeon Secondary Caches (L2C)" 367 depends on CAVIUM_OCTEON_SOC 368 help 369 Support for error detection and correction on the 370 Cavium Octeon family of SOCs. 371 372config EDAC_OCTEON_LMC 373 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 374 depends on CAVIUM_OCTEON_SOC 375 help 376 Support for error detection and correction on the 377 Cavium Octeon family of SOCs. 378 379config EDAC_OCTEON_PCI 380 tristate "Cavium Octeon PCI Controller" 381 depends on PCI && CAVIUM_OCTEON_SOC 382 help 383 Support for error detection and correction on the 384 Cavium Octeon family of SOCs. 385 386config EDAC_THUNDERX 387 tristate "Cavium ThunderX EDAC" 388 depends on ARM64 389 depends on PCI 390 help 391 Support for error detection and correction on the 392 Cavium ThunderX memory controllers (LMC), Cache 393 Coherent Processor Interconnect (CCPI) and L2 cache 394 blocks (TAD, CBC, MCI). 395 396config EDAC_ALTERA 397 bool "Altera SOCFPGA ECC" 398 depends on EDAC=y && ARCH_INTEL_SOCFPGA 399 help 400 Support for error detection and correction on the 401 Altera SOCs. This is the global enable for the 402 various Altera peripherals. 403 404config EDAC_ALTERA_SDRAM 405 bool "Altera SDRAM ECC" 406 depends on EDAC_ALTERA=y 407 help 408 Support for error detection and correction on the 409 Altera SDRAM Memory for Altera SoCs. Note that the 410 preloader must initialize the SDRAM before loading 411 the kernel. 412 413config EDAC_ALTERA_L2C 414 bool "Altera L2 Cache ECC" 415 depends on EDAC_ALTERA=y && CACHE_L2X0 416 help 417 Support for error detection and correction on the 418 Altera L2 cache Memory for Altera SoCs. This option 419 requires L2 cache. 420 421config EDAC_ALTERA_OCRAM 422 bool "Altera On-Chip RAM ECC" 423 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 424 help 425 Support for error detection and correction on the 426 Altera On-Chip RAM Memory for Altera SoCs. 427 428config EDAC_ALTERA_ETHERNET 429 bool "Altera Ethernet FIFO ECC" 430 depends on EDAC_ALTERA=y 431 help 432 Support for error detection and correction on the 433 Altera Ethernet FIFO Memory for Altera SoCs. 434 435config EDAC_ALTERA_NAND 436 bool "Altera NAND FIFO ECC" 437 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 438 help 439 Support for error detection and correction on the 440 Altera NAND FIFO Memory for Altera SoCs. 441 442config EDAC_ALTERA_DMA 443 bool "Altera DMA FIFO ECC" 444 depends on EDAC_ALTERA=y && PL330_DMA=y 445 help 446 Support for error detection and correction on the 447 Altera DMA FIFO Memory for Altera SoCs. 448 449config EDAC_ALTERA_USB 450 bool "Altera USB FIFO ECC" 451 depends on EDAC_ALTERA=y && USB_DWC2 452 help 453 Support for error detection and correction on the 454 Altera USB FIFO Memory for Altera SoCs. 455 456config EDAC_ALTERA_QSPI 457 bool "Altera QSPI FIFO ECC" 458 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 459 help 460 Support for error detection and correction on the 461 Altera QSPI FIFO Memory for Altera SoCs. 462 463config EDAC_ALTERA_SDMMC 464 bool "Altera SDMMC FIFO ECC" 465 depends on EDAC_ALTERA=y && MMC_DW 466 help 467 Support for error detection and correction on the 468 Altera SDMMC FIFO Memory for Altera SoCs. 469 470config EDAC_SIFIVE 471 bool "Sifive platform EDAC driver" 472 depends on EDAC=y && SIFIVE_CCACHE 473 help 474 Support for error detection and correction on the SiFive SoCs. 475 476config EDAC_ARMADA_XP 477 bool "Marvell Armada XP DDR and L2 Cache ECC" 478 depends on MACH_MVEBU_V7 479 help 480 Support for error correction and detection on the Marvell Aramada XP 481 DDR RAM and L2 cache controllers. 482 483config EDAC_SYNOPSYS 484 tristate "Synopsys DDR Memory Controller" 485 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 486 help 487 Support for error detection and correction on the Synopsys DDR 488 memory controller. 489 490config EDAC_XGENE 491 tristate "APM X-Gene SoC" 492 depends on (ARM64 || COMPILE_TEST) 493 help 494 Support for error detection and correction on the 495 APM X-Gene family of SOCs. 496 497config EDAC_TI 498 tristate "Texas Instruments DDR3 ECC Controller" 499 depends on ARCH_KEYSTONE || SOC_DRA7XX 500 help 501 Support for error detection and correction on the TI SoCs. 502 503config EDAC_QCOM 504 tristate "QCOM EDAC Controller" 505 depends on ARCH_QCOM && QCOM_LLCC 506 help 507 Support for error detection and correction on the 508 Qualcomm Technologies, Inc. SoCs. 509 510 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 511 As of now, it supports error reporting for Last Level Cache Controller (LLCC) 512 of Tag RAM and Data RAM. 513 514 For debugging issues having to do with stability and overall system 515 health, you should probably say 'Y' here. 516 517config EDAC_ASPEED 518 tristate "Aspeed AST BMC SoC" 519 depends on ARCH_ASPEED 520 help 521 Support for error detection and correction on the Aspeed AST BMC SoC. 522 523 First, ECC must be configured in the bootloader. Then, this driver 524 will expose error counters via the EDAC kernel framework. 525 526config EDAC_BLUEFIELD 527 tristate "Mellanox BlueField Memory ECC" 528 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 529 help 530 Support for error detection and correction on the 531 Mellanox BlueField SoCs. 532 533config EDAC_DMC520 534 tristate "ARM DMC-520 ECC" 535 depends on ARM64 536 help 537 Support for error detection and correction on the 538 SoCs with ARM DMC-520 DRAM controller. 539 540config EDAC_ZYNQMP 541 tristate "Xilinx ZynqMP OCM Controller" 542 depends on ARCH_ZYNQMP || COMPILE_TEST 543 help 544 This driver supports error detection and correction for the 545 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 546 built as a module. In that case it will be called zynqmp_edac. 547 548config EDAC_NPCM 549 tristate "Nuvoton NPCM DDR Memory Controller" 550 depends on (ARCH_NPCM || COMPILE_TEST) 551 help 552 Support for error detection and correction on the Nuvoton NPCM DDR 553 memory controller. 554 555 The memory controller supports single bit error correction, double bit 556 error detection (in-line ECC in which a section 1/8th of the memory 557 device used to store data is used for ECC storage). 558 559config EDAC_VERSAL 560 tristate "Xilinx Versal DDR Memory Controller" 561 depends on ARCH_ZYNQMP || COMPILE_TEST 562 help 563 Support for error detection and correction on the Xilinx Versal DDR 564 memory controller. 565 566 Report both single bit errors (CE) and double bit errors (UE). 567 Support injecting both correctable and uncorrectable errors 568 for debugging purposes. 569 570config EDAC_LOONGSON 571 tristate "Loongson Memory Controller" 572 depends on LOONGARCH && ACPI 573 help 574 Support for error detection and correction on the Loongson 575 family memory controller. This driver reports single bit 576 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000 577 are compatible. 578 579endif # EDAC 580