14640fa18SNava kishore Manne // SPDX-License-Identifier: GPL-2.0+
24640fa18SNava kishore Manne /*
34640fa18SNava kishore Manne * Copyright (C) 2019 Xilinx, Inc.
429be47fcSPraveen Teja Kundanala * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
54640fa18SNava kishore Manne */
64640fa18SNava kishore Manne
7*737c0c8dSPraveen Teja Kundanala #include <linux/dma-mapping.h>
84640fa18SNava kishore Manne #include <linux/module.h>
94640fa18SNava kishore Manne #include <linux/nvmem-provider.h>
104640fa18SNava kishore Manne #include <linux/of.h>
114640fa18SNava kishore Manne #include <linux/platform_device.h>
124640fa18SNava kishore Manne #include <linux/firmware/xlnx-zynqmp.h>
134640fa18SNava kishore Manne
144640fa18SNava kishore Manne #define SILICON_REVISION_MASK 0xF
15*737c0c8dSPraveen Teja Kundanala #define P_USER_0_64_UPPER_MASK GENMASK(31, 16)
16*737c0c8dSPraveen Teja Kundanala #define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)
17*737c0c8dSPraveen Teja Kundanala #define WORD_INBYTES 4
18*737c0c8dSPraveen Teja Kundanala #define SOC_VER_SIZE 0x4
19*737c0c8dSPraveen Teja Kundanala #define EFUSE_MEMORY_SIZE 0x177
20*737c0c8dSPraveen Teja Kundanala #define UNUSED_SPACE 0x8
21*737c0c8dSPraveen Teja Kundanala #define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \
22*737c0c8dSPraveen Teja Kundanala EFUSE_MEMORY_SIZE)
23*737c0c8dSPraveen Teja Kundanala #define SOC_VERSION_OFFSET 0x0
24*737c0c8dSPraveen Teja Kundanala #define EFUSE_START_OFFSET 0xC
25*737c0c8dSPraveen Teja Kundanala #define EFUSE_END_OFFSET 0xFC
26*737c0c8dSPraveen Teja Kundanala #define EFUSE_PUF_START_OFFSET 0x100
27*737c0c8dSPraveen Teja Kundanala #define EFUSE_PUF_MID_OFFSET 0x140
28*737c0c8dSPraveen Teja Kundanala #define EFUSE_PUF_END_OFFSET 0x17F
29*737c0c8dSPraveen Teja Kundanala #define EFUSE_NOT_ENABLED 29
304640fa18SNava kishore Manne
31*737c0c8dSPraveen Teja Kundanala /*
32*737c0c8dSPraveen Teja Kundanala * efuse access type
33*737c0c8dSPraveen Teja Kundanala */
34*737c0c8dSPraveen Teja Kundanala enum efuse_access {
35*737c0c8dSPraveen Teja Kundanala EFUSE_READ = 0,
36*737c0c8dSPraveen Teja Kundanala EFUSE_WRITE
37*737c0c8dSPraveen Teja Kundanala };
384640fa18SNava kishore Manne
39*737c0c8dSPraveen Teja Kundanala /**
40*737c0c8dSPraveen Teja Kundanala * struct xilinx_efuse - the basic structure
41*737c0c8dSPraveen Teja Kundanala * @src: address of the buffer to store the data to be write/read
42*737c0c8dSPraveen Teja Kundanala * @size: read/write word count
43*737c0c8dSPraveen Teja Kundanala * @offset: read/write offset
44*737c0c8dSPraveen Teja Kundanala * @flag: 0 - represents efuse read and 1- represents efuse write
45*737c0c8dSPraveen Teja Kundanala * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
46*737c0c8dSPraveen Teja Kundanala * 1 - represents puf user fuse row number.
47*737c0c8dSPraveen Teja Kundanala *
48*737c0c8dSPraveen Teja Kundanala * this structure stores all the required details to
49*737c0c8dSPraveen Teja Kundanala * read/write efuse memory.
50*737c0c8dSPraveen Teja Kundanala */
51*737c0c8dSPraveen Teja Kundanala struct xilinx_efuse {
52*737c0c8dSPraveen Teja Kundanala u64 src;
53*737c0c8dSPraveen Teja Kundanala u32 size;
54*737c0c8dSPraveen Teja Kundanala u32 offset;
55*737c0c8dSPraveen Teja Kundanala enum efuse_access flag;
56*737c0c8dSPraveen Teja Kundanala u32 pufuserfuse;
57*737c0c8dSPraveen Teja Kundanala };
58*737c0c8dSPraveen Teja Kundanala
zynqmp_efuse_access(void * context,unsigned int offset,void * val,size_t bytes,enum efuse_access flag,unsigned int pufflag)59*737c0c8dSPraveen Teja Kundanala static int zynqmp_efuse_access(void *context, unsigned int offset,
60*737c0c8dSPraveen Teja Kundanala void *val, size_t bytes, enum efuse_access flag,
61*737c0c8dSPraveen Teja Kundanala unsigned int pufflag)
62*737c0c8dSPraveen Teja Kundanala {
63*737c0c8dSPraveen Teja Kundanala struct device *dev = context;
64*737c0c8dSPraveen Teja Kundanala struct xilinx_efuse *efuse;
65*737c0c8dSPraveen Teja Kundanala dma_addr_t dma_addr;
66*737c0c8dSPraveen Teja Kundanala dma_addr_t dma_buf;
67*737c0c8dSPraveen Teja Kundanala size_t words = bytes / WORD_INBYTES;
68*737c0c8dSPraveen Teja Kundanala int ret;
69*737c0c8dSPraveen Teja Kundanala int value;
70*737c0c8dSPraveen Teja Kundanala char *data;
71*737c0c8dSPraveen Teja Kundanala
72*737c0c8dSPraveen Teja Kundanala if (bytes % WORD_INBYTES != 0) {
73*737c0c8dSPraveen Teja Kundanala dev_err(dev, "Bytes requested should be word aligned\n");
74*737c0c8dSPraveen Teja Kundanala return -EOPNOTSUPP;
75*737c0c8dSPraveen Teja Kundanala }
76*737c0c8dSPraveen Teja Kundanala
77*737c0c8dSPraveen Teja Kundanala if (pufflag == 0 && offset % WORD_INBYTES) {
78*737c0c8dSPraveen Teja Kundanala dev_err(dev, "Offset requested should be word aligned\n");
79*737c0c8dSPraveen Teja Kundanala return -EOPNOTSUPP;
80*737c0c8dSPraveen Teja Kundanala }
81*737c0c8dSPraveen Teja Kundanala
82*737c0c8dSPraveen Teja Kundanala if (pufflag == 1 && flag == EFUSE_WRITE) {
83*737c0c8dSPraveen Teja Kundanala memcpy(&value, val, bytes);
84*737c0c8dSPraveen Teja Kundanala if ((offset == EFUSE_PUF_START_OFFSET ||
85*737c0c8dSPraveen Teja Kundanala offset == EFUSE_PUF_MID_OFFSET) &&
86*737c0c8dSPraveen Teja Kundanala value & P_USER_0_64_UPPER_MASK) {
87*737c0c8dSPraveen Teja Kundanala dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER_0 & P_USER_64\n");
88*737c0c8dSPraveen Teja Kundanala return -EOPNOTSUPP;
89*737c0c8dSPraveen Teja Kundanala }
90*737c0c8dSPraveen Teja Kundanala
91*737c0c8dSPraveen Teja Kundanala if (offset == EFUSE_PUF_END_OFFSET &&
92*737c0c8dSPraveen Teja Kundanala (value & P_USER_127_LOWER_4_BIT_MASK)) {
93*737c0c8dSPraveen Teja Kundanala dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_127\n");
94*737c0c8dSPraveen Teja Kundanala return -EOPNOTSUPP;
95*737c0c8dSPraveen Teja Kundanala }
96*737c0c8dSPraveen Teja Kundanala }
97*737c0c8dSPraveen Teja Kundanala
98*737c0c8dSPraveen Teja Kundanala efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse),
99*737c0c8dSPraveen Teja Kundanala &dma_addr, GFP_KERNEL);
100*737c0c8dSPraveen Teja Kundanala if (!efuse)
101*737c0c8dSPraveen Teja Kundanala return -ENOMEM;
102*737c0c8dSPraveen Teja Kundanala
103*737c0c8dSPraveen Teja Kundanala data = dma_alloc_coherent(dev, sizeof(bytes),
104*737c0c8dSPraveen Teja Kundanala &dma_buf, GFP_KERNEL);
105*737c0c8dSPraveen Teja Kundanala if (!data) {
106*737c0c8dSPraveen Teja Kundanala ret = -ENOMEM;
107*737c0c8dSPraveen Teja Kundanala goto efuse_data_fail;
108*737c0c8dSPraveen Teja Kundanala }
109*737c0c8dSPraveen Teja Kundanala
110*737c0c8dSPraveen Teja Kundanala if (flag == EFUSE_WRITE) {
111*737c0c8dSPraveen Teja Kundanala memcpy(data, val, bytes);
112*737c0c8dSPraveen Teja Kundanala efuse->flag = EFUSE_WRITE;
113*737c0c8dSPraveen Teja Kundanala } else {
114*737c0c8dSPraveen Teja Kundanala efuse->flag = EFUSE_READ;
115*737c0c8dSPraveen Teja Kundanala }
116*737c0c8dSPraveen Teja Kundanala
117*737c0c8dSPraveen Teja Kundanala efuse->src = dma_buf;
118*737c0c8dSPraveen Teja Kundanala efuse->size = words;
119*737c0c8dSPraveen Teja Kundanala efuse->offset = offset;
120*737c0c8dSPraveen Teja Kundanala efuse->pufuserfuse = pufflag;
121*737c0c8dSPraveen Teja Kundanala
122*737c0c8dSPraveen Teja Kundanala zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret);
123*737c0c8dSPraveen Teja Kundanala if (ret != 0) {
124*737c0c8dSPraveen Teja Kundanala if (ret == EFUSE_NOT_ENABLED) {
125*737c0c8dSPraveen Teja Kundanala dev_err(dev, "efuse access is not enabled\n");
126*737c0c8dSPraveen Teja Kundanala ret = -EOPNOTSUPP;
127*737c0c8dSPraveen Teja Kundanala } else {
128*737c0c8dSPraveen Teja Kundanala dev_err(dev, "Error in efuse read %x\n", ret);
129*737c0c8dSPraveen Teja Kundanala ret = -EPERM;
130*737c0c8dSPraveen Teja Kundanala }
131*737c0c8dSPraveen Teja Kundanala goto efuse_access_err;
132*737c0c8dSPraveen Teja Kundanala }
133*737c0c8dSPraveen Teja Kundanala
134*737c0c8dSPraveen Teja Kundanala if (flag == EFUSE_READ)
135*737c0c8dSPraveen Teja Kundanala memcpy(val, data, bytes);
136*737c0c8dSPraveen Teja Kundanala efuse_access_err:
137*737c0c8dSPraveen Teja Kundanala dma_free_coherent(dev, sizeof(bytes),
138*737c0c8dSPraveen Teja Kundanala data, dma_buf);
139*737c0c8dSPraveen Teja Kundanala efuse_data_fail:
140*737c0c8dSPraveen Teja Kundanala dma_free_coherent(dev, sizeof(struct xilinx_efuse),
141*737c0c8dSPraveen Teja Kundanala efuse, dma_addr);
142*737c0c8dSPraveen Teja Kundanala
143*737c0c8dSPraveen Teja Kundanala return ret;
144*737c0c8dSPraveen Teja Kundanala }
145*737c0c8dSPraveen Teja Kundanala
zynqmp_nvmem_read(void * context,unsigned int offset,void * val,size_t bytes)146*737c0c8dSPraveen Teja Kundanala static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes)
1474640fa18SNava kishore Manne {
14829be47fcSPraveen Teja Kundanala struct device *dev = context;
1494640fa18SNava kishore Manne int ret;
150*737c0c8dSPraveen Teja Kundanala int pufflag = 0;
15129be47fcSPraveen Teja Kundanala int idcode;
15229be47fcSPraveen Teja Kundanala int version;
1534640fa18SNava kishore Manne
154*737c0c8dSPraveen Teja Kundanala if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
155*737c0c8dSPraveen Teja Kundanala pufflag = 1;
156*737c0c8dSPraveen Teja Kundanala
157*737c0c8dSPraveen Teja Kundanala switch (offset) {
158*737c0c8dSPraveen Teja Kundanala /* Soc version offset is zero */
159*737c0c8dSPraveen Teja Kundanala case SOC_VERSION_OFFSET:
160*737c0c8dSPraveen Teja Kundanala if (bytes != SOC_VER_SIZE)
161*737c0c8dSPraveen Teja Kundanala return -EOPNOTSUPP;
162*737c0c8dSPraveen Teja Kundanala
163*737c0c8dSPraveen Teja Kundanala ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version);
1644640fa18SNava kishore Manne if (ret < 0)
1654640fa18SNava kishore Manne return ret;
1664640fa18SNava kishore Manne
16729be47fcSPraveen Teja Kundanala dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
1684640fa18SNava kishore Manne *(int *)val = version & SILICON_REVISION_MASK;
169*737c0c8dSPraveen Teja Kundanala break;
170*737c0c8dSPraveen Teja Kundanala /* Efuse offset starts from 0xc */
171*737c0c8dSPraveen Teja Kundanala case EFUSE_START_OFFSET ... EFUSE_END_OFFSET:
172*737c0c8dSPraveen Teja Kundanala case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET:
173*737c0c8dSPraveen Teja Kundanala ret = zynqmp_efuse_access(context, offset, val,
174*737c0c8dSPraveen Teja Kundanala bytes, EFUSE_READ, pufflag);
175*737c0c8dSPraveen Teja Kundanala break;
176*737c0c8dSPraveen Teja Kundanala default:
177*737c0c8dSPraveen Teja Kundanala *(u32 *)val = 0xDEADBEEF;
178*737c0c8dSPraveen Teja Kundanala ret = 0;
179*737c0c8dSPraveen Teja Kundanala break;
180*737c0c8dSPraveen Teja Kundanala }
1814640fa18SNava kishore Manne
182*737c0c8dSPraveen Teja Kundanala return ret;
183*737c0c8dSPraveen Teja Kundanala }
184*737c0c8dSPraveen Teja Kundanala
zynqmp_nvmem_write(void * context,unsigned int offset,void * val,size_t bytes)185*737c0c8dSPraveen Teja Kundanala static int zynqmp_nvmem_write(void *context,
186*737c0c8dSPraveen Teja Kundanala unsigned int offset, void *val, size_t bytes)
187*737c0c8dSPraveen Teja Kundanala {
188*737c0c8dSPraveen Teja Kundanala int pufflag = 0;
189*737c0c8dSPraveen Teja Kundanala
190*737c0c8dSPraveen Teja Kundanala if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET)
191*737c0c8dSPraveen Teja Kundanala return -EOPNOTSUPP;
192*737c0c8dSPraveen Teja Kundanala
193*737c0c8dSPraveen Teja Kundanala if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
194*737c0c8dSPraveen Teja Kundanala pufflag = 1;
195*737c0c8dSPraveen Teja Kundanala
196*737c0c8dSPraveen Teja Kundanala return zynqmp_efuse_access(context, offset,
197*737c0c8dSPraveen Teja Kundanala val, bytes, EFUSE_WRITE, pufflag);
1984640fa18SNava kishore Manne }
1994640fa18SNava kishore Manne
2004640fa18SNava kishore Manne static const struct of_device_id zynqmp_nvmem_match[] = {
2014640fa18SNava kishore Manne { .compatible = "xlnx,zynqmp-nvmem-fw", },
2024640fa18SNava kishore Manne { /* sentinel */ },
2034640fa18SNava kishore Manne };
2044640fa18SNava kishore Manne MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match);
2054640fa18SNava kishore Manne
zynqmp_nvmem_probe(struct platform_device * pdev)2064640fa18SNava kishore Manne static int zynqmp_nvmem_probe(struct platform_device *pdev)
2074640fa18SNava kishore Manne {
2084640fa18SNava kishore Manne struct device *dev = &pdev->dev;
20929be47fcSPraveen Teja Kundanala struct nvmem_config econfig = {};
2104640fa18SNava kishore Manne
21129be47fcSPraveen Teja Kundanala econfig.name = "zynqmp-nvmem";
21229be47fcSPraveen Teja Kundanala econfig.owner = THIS_MODULE;
21329be47fcSPraveen Teja Kundanala econfig.word_size = 1;
214*737c0c8dSPraveen Teja Kundanala econfig.size = ZYNQMP_NVMEM_SIZE;
2154640fa18SNava kishore Manne econfig.dev = dev;
2162cc3b37fSRafał Miłecki econfig.add_legacy_fixed_of_cells = true;
2174640fa18SNava kishore Manne econfig.reg_read = zynqmp_nvmem_read;
218*737c0c8dSPraveen Teja Kundanala econfig.reg_write = zynqmp_nvmem_write;
2194640fa18SNava kishore Manne
22029be47fcSPraveen Teja Kundanala return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));
2214640fa18SNava kishore Manne }
2224640fa18SNava kishore Manne
2234640fa18SNava kishore Manne static struct platform_driver zynqmp_nvmem_driver = {
2244640fa18SNava kishore Manne .probe = zynqmp_nvmem_probe,
2254640fa18SNava kishore Manne .driver = {
2264640fa18SNava kishore Manne .name = "zynqmp-nvmem",
2274640fa18SNava kishore Manne .of_match_table = zynqmp_nvmem_match,
2284640fa18SNava kishore Manne },
2294640fa18SNava kishore Manne };
2304640fa18SNava kishore Manne
2314640fa18SNava kishore Manne module_platform_driver(zynqmp_nvmem_driver);
2324640fa18SNava kishore Manne
23397344089SMichal Simek MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>, Nava kishore Manne <nava.kishore.manne@amd.com>");
2344640fa18SNava kishore Manne MODULE_DESCRIPTION("ZynqMP NVMEM driver");
2354640fa18SNava kishore Manne MODULE_LICENSE("GPL");
236