xref: /linux/drivers/fpga/zynqmp-fpga.c (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2019 Xilinx, Inc.
4  */
5 
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/string.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
14 
15 /* Constant Definitions */
16 #define IXR_FPGA_DONE_MASK	BIT(3)
17 
18 /**
19  * struct zynqmp_fpga_priv - Private data structure
20  * @dev:	Device data structure
21  * @flags:	flags which is used to identify the bitfile type
22  */
23 struct zynqmp_fpga_priv {
24 	struct device *dev;
25 	u32 flags;
26 };
27 
zynqmp_fpga_ops_write_init(struct fpga_manager * mgr,struct fpga_image_info * info,const char * buf,size_t size)28 static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
29 				      struct fpga_image_info *info,
30 				      const char *buf, size_t size)
31 {
32 	struct zynqmp_fpga_priv *priv;
33 
34 	priv = mgr->priv;
35 	priv->flags = info->flags;
36 
37 	return 0;
38 }
39 
zynqmp_fpga_ops_write(struct fpga_manager * mgr,const char * buf,size_t size)40 static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
41 				 const char *buf, size_t size)
42 {
43 	struct zynqmp_fpga_priv *priv;
44 	dma_addr_t dma_addr;
45 	u32 eemi_flags = 0;
46 	char *kbuf;
47 	int ret;
48 
49 	priv = mgr->priv;
50 
51 	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
52 	if (!kbuf)
53 		return -ENOMEM;
54 
55 	memcpy(kbuf, buf, size);
56 
57 	wmb(); /* ensure all writes are done before initiate FW call */
58 
59 	if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
60 		eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
61 
62 	ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags);
63 
64 	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
65 
66 	return ret;
67 }
68 
zynqmp_fpga_ops_state(struct fpga_manager * mgr)69 static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
70 {
71 	u32 status = 0;
72 
73 	zynqmp_pm_fpga_get_status(&status);
74 	if (status & IXR_FPGA_DONE_MASK)
75 		return FPGA_MGR_STATE_OPERATING;
76 
77 	return FPGA_MGR_STATE_UNKNOWN;
78 }
79 
status_show(struct device * dev,struct device_attribute * attr,char * buf)80 static ssize_t status_show(struct device *dev,
81 			   struct device_attribute *attr, char *buf)
82 {
83 	u32 status;
84 	int ret;
85 
86 	ret = zynqmp_pm_fpga_get_config_status(&status);
87 	if (ret)
88 		return ret;
89 
90 	return sysfs_emit(buf, "0x%x\n", status);
91 }
92 static DEVICE_ATTR_RO(status);
93 
94 static struct attribute *zynqmp_fpga_attrs[] = {
95 	&dev_attr_status.attr,
96 	NULL,
97 };
98 ATTRIBUTE_GROUPS(zynqmp_fpga);
99 
100 static const struct fpga_manager_ops zynqmp_fpga_ops = {
101 	.state = zynqmp_fpga_ops_state,
102 	.write_init = zynqmp_fpga_ops_write_init,
103 	.write = zynqmp_fpga_ops_write,
104 };
105 
zynqmp_fpga_probe(struct platform_device * pdev)106 static int zynqmp_fpga_probe(struct platform_device *pdev)
107 {
108 	struct device *dev = &pdev->dev;
109 	struct zynqmp_fpga_priv *priv;
110 	struct fpga_manager *mgr;
111 
112 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
113 	if (!priv)
114 		return -ENOMEM;
115 
116 	priv->dev = dev;
117 
118 	mgr = devm_fpga_mgr_register(dev, "Xilinx ZynqMP FPGA Manager",
119 				     &zynqmp_fpga_ops, priv);
120 	return PTR_ERR_OR_ZERO(mgr);
121 }
122 
123 #ifdef CONFIG_OF
124 static const struct of_device_id zynqmp_fpga_of_match[] = {
125 	{ .compatible = "xlnx,zynqmp-pcap-fpga", },
126 	{},
127 };
128 MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
129 #endif
130 
131 static struct platform_driver zynqmp_fpga_driver = {
132 	.probe = zynqmp_fpga_probe,
133 	.driver = {
134 		.name = "zynqmp_fpga_manager",
135 		.of_match_table = of_match_ptr(zynqmp_fpga_of_match),
136 		.dev_groups = zynqmp_fpga_groups,
137 	},
138 };
139 
140 module_platform_driver(zynqmp_fpga_driver);
141 
142 MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
143 MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
144 MODULE_LICENSE("GPL");
145