1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx R5F processor subsystem 8 9maintainers: 10 - Ben Levinsky <ben.levinsky@amd.com> 11 - Tanmay Shah <tanmay.shah@amd.com> 12 13description: | 14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for 15 real-time processing based on the Cortex-R5F processor core from ARM. 16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a 17 floating-point unit that implements the Arm VFPv3 instruction set. 18 19properties: 20 compatible: 21 enum: 22 - xlnx,zynqmp-r5fss 23 - xlnx,versal-r5fss 24 - xlnx,versal-net-r52fss 25 26 "#address-cells": 27 const: 2 28 29 "#size-cells": 30 const: 2 31 32 ranges: 33 description: | 34 Standard ranges definition providing address translations for 35 local R5F TCM address spaces to bus addresses. 36 37 xlnx,cluster-mode: 38 $ref: /schemas/types.yaml#/definitions/uint32 39 enum: [0, 1, 2] 40 default: 1 41 description: | 42 The RPU MPCore can operate in split mode (Dual-processor performance), Safety 43 lock-step mode(Both RPU cores execute the same code in lock-step, 44 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while 45 core 1 runs normally). The processor does not support dynamic configuration. 46 Switching between modes is only permitted immediately after a processor reset. 47 If set to 1 then lockstep mode and if 0 then split mode. 48 If set to 2 then single CPU mode. When not defined, default will be lockstep mode. 49 In summary, 50 0: split mode 51 1: lockstep mode (default) 52 2: single cpu mode 53 54 xlnx,tcm-mode: 55 $ref: /schemas/types.yaml#/definitions/uint32 56 enum: [0, 1] 57 description: | 58 Configure RPU TCM 59 0: split mode 60 1: lockstep mode 61 62patternProperties: 63 "^r(.*)@[0-9a-f]+$": 64 type: object 65 additionalProperties: false 66 description: | 67 The RPU is located in the Low Power Domain of the Processor Subsystem. 68 Each processor includes separate L1 instruction and data caches and 69 tightly coupled memories (TCM). System memory is cacheable, but the TCM 70 memory space is non-cacheable. 71 72 Each RPU contains one 64KB memory and two 32KB memories that 73 are accessed via the TCM A and B port interfaces, for a total of 128KB 74 per processor. In lock-step mode, the processor has access to 256KB of 75 TCM memory. 76 77 properties: 78 compatible: 79 enum: 80 - xlnx,zynqmp-r5f 81 - xlnx,versal-r5f 82 - xlnx,versal-net-r52f 83 84 reg: 85 minItems: 1 86 maxItems: 4 87 88 reg-names: 89 minItems: 1 90 maxItems: 4 91 92 power-domains: 93 minItems: 2 94 maxItems: 5 95 96 mboxes: 97 minItems: 1 98 items: 99 - description: mailbox channel to send data to RPU 100 - description: mailbox channel to receive data from RPU 101 102 mbox-names: 103 minItems: 1 104 items: 105 - const: tx 106 - const: rx 107 108 sram: 109 $ref: /schemas/types.yaml#/definitions/phandle-array 110 minItems: 1 111 maxItems: 8 112 items: 113 maxItems: 1 114 description: | 115 phandles to one or more reserved on-chip SRAM regions. Other than TCM, 116 the RPU can execute instructions and access data from the OCM memory, 117 the main DDR memory, and other system memories. 118 119 The regions should be defined as child nodes of the respective SRAM 120 node, and should be defined as per the generic bindings in 121 Documentation/devicetree/bindings/sram/sram.yaml 122 123 memory-region: 124 description: | 125 List of phandles to the reserved memory regions associated with the 126 remoteproc device. This is variable and describes the memories shared with 127 the remote processor (e.g. remoteproc firmware and carveouts, rpmsg 128 vrings, ...). This reserved memory region will be allocated in DDR memory. 129 minItems: 1 130 maxItems: 8 131 items: 132 - description: region used for RPU firmware image section 133 - description: vdev buffer 134 - description: vring0 135 - description: vring1 136 additionalItems: true 137 138 required: 139 - compatible 140 - reg 141 - reg-names 142 - power-domains 143 144required: 145 - compatible 146 - "#address-cells" 147 - "#size-cells" 148 - ranges 149 150allOf: 151 - if: 152 properties: 153 compatible: 154 contains: 155 enum: 156 - xlnx,versal-net-r52fss 157 then: 158 properties: 159 xlnx,tcm-mode: false 160 161 patternProperties: 162 "^r52f@[0-9a-f]+$": 163 type: object 164 165 properties: 166 reg: 167 minItems: 1 168 items: 169 - description: ATCM internal memory 170 - description: BTCM internal memory 171 - description: CTCM internal memory 172 173 reg-names: 174 minItems: 1 175 items: 176 - const: atcm0 177 - const: btcm0 178 - const: ctcm0 179 180 power-domains: 181 minItems: 2 182 items: 183 - description: RPU core power domain 184 - description: ATCM power domain 185 - description: BTCM power domain 186 - description: CTCM power domain 187 188 - if: 189 properties: 190 compatible: 191 contains: 192 enum: 193 - xlnx,zynqmp-r5fss 194 - xlnx,versal-r5fss 195 then: 196 if: 197 properties: 198 xlnx,cluster-mode: 199 enum: [1, 2] 200 then: 201 properties: 202 xlnx,tcm-mode: 203 enum: [1] 204 205 patternProperties: 206 "^r5f@[0-9a-f]+$": 207 type: object 208 209 properties: 210 reg: 211 minItems: 1 212 items: 213 - description: ATCM internal memory 214 - description: BTCM internal memory 215 - description: extra ATCM memory in lockstep mode 216 - description: extra BTCM memory in lockstep mode 217 218 reg-names: 219 minItems: 1 220 items: 221 - const: atcm0 222 - const: btcm0 223 - const: atcm1 224 - const: btcm1 225 226 power-domains: 227 minItems: 2 228 items: 229 - description: RPU core power domain 230 - description: ATCM power domain 231 - description: BTCM power domain 232 - description: second ATCM power domain 233 - description: second BTCM power domain 234 235 required: 236 - xlnx,tcm-mode 237 238 else: 239 properties: 240 xlnx,tcm-mode: 241 enum: [0] 242 243 patternProperties: 244 "^r5f@[0-9a-f]+$": 245 type: object 246 247 properties: 248 reg: 249 minItems: 1 250 items: 251 - description: ATCM internal memory 252 - description: BTCM internal memory 253 254 reg-names: 255 minItems: 1 256 items: 257 - const: atcm0 258 - const: btcm0 259 260 power-domains: 261 minItems: 2 262 items: 263 - description: RPU core power domain 264 - description: ATCM power domain 265 - description: BTCM power domain 266 267 required: 268 - xlnx,tcm-mode 269 270additionalProperties: false 271 272examples: 273 - | 274 #include <dt-bindings/power/xlnx-zynqmp-power.h> 275 276 // Split mode configuration 277 soc { 278 #address-cells = <2>; 279 #size-cells = <2>; 280 281 remoteproc@ffe00000 { 282 compatible = "xlnx,zynqmp-r5fss"; 283 xlnx,cluster-mode = <0>; 284 xlnx,tcm-mode = <0>; 285 286 #address-cells = <2>; 287 #size-cells = <2>; 288 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 289 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 290 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, 291 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; 292 293 r5f@0 { 294 compatible = "xlnx,zynqmp-r5f"; 295 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; 296 reg-names = "atcm0", "btcm0"; 297 power-domains = <&zynqmp_firmware PD_RPU_0>, 298 <&zynqmp_firmware PD_R5_0_ATCM>, 299 <&zynqmp_firmware PD_R5_0_BTCM>; 300 memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, 301 <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; 302 mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; 303 mbox-names = "tx", "rx"; 304 }; 305 306 r5f@1 { 307 compatible = "xlnx,zynqmp-r5f"; 308 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 309 reg-names = "atcm0", "btcm0"; 310 power-domains = <&zynqmp_firmware PD_RPU_1>, 311 <&zynqmp_firmware PD_R5_1_ATCM>, 312 <&zynqmp_firmware PD_R5_1_BTCM>; 313 memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, 314 <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; 315 mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; 316 mbox-names = "tx", "rx"; 317 }; 318 }; 319 }; 320 321 - | 322 //Lockstep configuration 323 soc { 324 #address-cells = <2>; 325 #size-cells = <2>; 326 327 remoteproc@ffe00000 { 328 compatible = "xlnx,zynqmp-r5fss"; 329 xlnx,cluster-mode = <1>; 330 xlnx,tcm-mode = <1>; 331 332 #address-cells = <2>; 333 #size-cells = <2>; 334 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 335 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 336 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, 337 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; 338 339 r5f@0 { 340 compatible = "xlnx,zynqmp-r5f"; 341 reg = <0x0 0x0 0x0 0x10000>, 342 <0x0 0x20000 0x0 0x10000>, 343 <0x0 0x10000 0x0 0x10000>, 344 <0x0 0x30000 0x0 0x10000>; 345 reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; 346 power-domains = <&zynqmp_firmware PD_RPU_0>, 347 <&zynqmp_firmware PD_R5_0_ATCM>, 348 <&zynqmp_firmware PD_R5_0_BTCM>, 349 <&zynqmp_firmware PD_R5_1_ATCM>, 350 <&zynqmp_firmware PD_R5_1_BTCM>; 351 memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, 352 <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; 353 mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; 354 mbox-names = "tx", "rx"; 355 }; 356 357 r5f@1 { 358 compatible = "xlnx,zynqmp-r5f"; 359 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 360 reg-names = "atcm0", "btcm0"; 361 power-domains = <&zynqmp_firmware PD_RPU_1>, 362 <&zynqmp_firmware PD_R5_1_ATCM>, 363 <&zynqmp_firmware PD_R5_1_BTCM>; 364 memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, 365 <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; 366 mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; 367 mbox-names = "tx", "rx"; 368 }; 369 }; 370 }; 371... 372