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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-zynq.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq GPIO controller
10 - Michal Simek <michal.simek@amd.com>
15 - xlnx,zynq-gpio-1.0
16 - xlnx,zynqmp-gpio-1.0
17 - xlnx,versal-gpio-1.0
18 - xlnx,pmc-gpio-1.0
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zybo-z7.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "zynq-7000.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
8 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
24 stdout-path = "serial0:115200n8";
27 gpio-leds {
28 compatible = "gpio-leds";
30 led-ld4 {
31 label = "zynq-zybo-z7:green:ld4";
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H A Dzynq-zturn-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Based on zynq-zed.dts which is:
7 * Copyright (C) 2011 - 2014 Xilinx
12 /dts-v1/;
13 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-7000";
31 stdout-path = "serial0:115200n8";
34 gpio-leds {
35 compatible = "gpio-leds";
36 usr-led1 {
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H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 u-boot {
13 compatible = "u-boot,config";
14 bootscr-address = /bits/ 64 <0x3000000>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
31 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
37 switch-14 {
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
40 ps-clk-frequency = <33333333>;
45 phy-mode = "rgmii-id";
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/linux/drivers/gpio/
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
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/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
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/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
90 tristate "GPIO reset controller"
94 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
97 If compiled as module, it will be called reset-gpio.
146 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
155 Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
231 Raspberry Pi 4's co-processor controls some of the board's HW
234 interfacing with RPi4's co-processor and model these firmware
272 - Altera SoCFPGAs
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
10 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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/linux/drivers/tty/serial/
H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
25 #include <linux/gpio.h>
26 #include <linux/gpio/consumer.h>
41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
189 * struct cdns_uart - device data
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/linux/drivers/spi/
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
12 #include <linux/gpio/consumer.h>
25 #define CDNS_SPI_NAME "cdns-spi"
63 * SPI Configuration Register - Baud rate and target select
102 * struct cdns_spi - This definition defines spi driver instance
136 return readl_relaxed(xspi->regs + offset); in cdns_spi_read()
141 writel_relaxed(val, xspi->regs + offset); in cdns_spi_write()
145 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/drivers/video/fbdev/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 a well-defined interface, so the software doesn't need to know
15 anything about the low-level (hardware register) stuff.
21 On several non-X86 architectures, the frame buffer device is the
29 and the Framebuffer-HOWTO at
30 <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more
40 are compiling a kernel for a non-x86 architecture.
46 device-aware may cause unexpected results. If unsure, say N.
57 Common utility functions useful to fbdev drivers of VGA-based
82 If you have a PCI-based system, this enables support for these
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/linux/drivers/i2c/busses/
H A Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3)
123 #define DRIVER_NAME "cdns-i2c"
135 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
136 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
140 * enum cdns_i2c_mode - I2C Controller current operating mode
151 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode
165 * struct cdns_i2c - I2C device private data structure
186 * @rinfo: I2C GPIO recovery information
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